Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
267
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.2.88 DMISTS
14.2.89 ERRINJCAP
PCI Express Error Injection Capability.
Defines a vendor specific capability for WHEA error injection.
0:0
RW
0x1
abort_inbound_requests:
Setting this bit causes IIO to abort all inbound requests on the DMI port. This 
will be used during specific power state and reset transitions to prevent 
requests from PCH. This bit does not apply in PCI Express mode. 
Inbound posted requests will be dropped and inbound nonposted requests 
will be completed with Unsupported Request completion. Completions flowing 
inbound (from outbound requests) will not be dropped, but will be forwarded 
normally. This bit will not affect S-state auto-completion, if it is enabled. 
Note: Requires CPU reset sequence to be completed.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (DMI2 Mode)
Offset:
0x1a8
Bit
Attr
Default
Description
31:1
RO
0x0
reserved:
0:0
RW1C
0x0
received_cpu_reset_done_ack:
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (DMI2 Mode)
Offset:
0x1a0
Bit
Attr
Default
Description
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x1d0
Bit
Attr
Default
Description
31:20
RO
0x250
0x280 (Device 0 Function 0)
nxtptr:
Next Capability Offset  
This field points to the next capability or 0 if there isn’t a 
next capability.
19:16
RO
0x1
capver:
Capability Version.
Set to 1h for this version of the PCI Express specification
15:0
RO
0xb
extcapid:
PCI Express Extended Capability ID  
Vendor Defined Capability
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