Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
333
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.4.39 CHANERRPTR
DMA Channel Error Pointer.
14.5
Device 4 Function 0 - 7 MMIO Region CB_BARs
Intel® Quick Data MMIO Register used to control the DMA functionality. The CB_BAR 
register points to the based address to these registers. 
All of these registers are accessible from only the processor. The IIO supports accessing 
the Intel® Quick Data device memory-mapped registers via QWORD reads and writes. 
The offsets indicated in the following table are from the CB_BAR value.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
4Function:0-7
Offset:
0x18c
Bit
Attr
Default
Description
7:5
RV
-
Reserved. 
4:0
ROS_V
0x0
dma_chan_err_pointer:
Points to the first uncorrectable, unmasked error logged in the 
CHANERR_INT register. This register is only valid when the corresponding 
error is unmasked and its status bit is set and this register is rearmed to load 
again once the error pointed to by this register, in the CHANERR_INT status 
register, is cleared.
Register name
Offset
Size
CHANCNT
0x0
8
XFERCAP
0x1
8
GENCTRL
0x2
8
INTRCTRL
0x3
8
ATTNSTATUS
0x4
32
CBVER
0x8
8
INTRDELAY
0xc
16
CS_STATUS
0xe
16
DMACAPABILITY
0x10
32
DCAOFFSET
0x14
16
CBPRIO
0x40
8
CHANCTRL
0x80
16
DMA_COMP
0x82
16
CHANCMD
0x84
8
DMACOUNT
0x86
16
CHANSTS_0
0x88
32
CHANSTS_1
0x8c
32
CHAINADDR_0
0x90
32
CHAINADDR_1
0x94
32
CHANCMP_0
0x98
32
CHANCMP_1
0x9c
32
CHANERR
0xa8
32
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