Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
334
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.5.1
CHANCNT
Channel Count.
The Channel Count register specifies the number of channels that are implemented.
CHANERRMSK
0xac
32
DCACTRL
0xb0
32
DCA_VER
0x100
8
DCA_REQID_OFFSET
0x102
16
QPI_CAPABILITY
0x108
16
PCIE_CAPABILITY
0x10a
16
QPI_CAP_ENABLE
0x10c
16
PCIE_CAP_ENABLE
0x10e
16
APICID_TAG_MAP
0x110
64
DCA_REQID0
0x180
32
DCA_REQID1
0x184
32
MSGADDR
0x2000
32
MSGUPADDR
0x2004
32
MSGDATA
0x2008
32
VECCTRL
0x200c
32
PENDINGBITS
0x3000
32
Register name
Offset
Size
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
4Function:0-7
Offset:
0x0
Bit
Attr
Default
Description
7:5
RV
-
Reserved. 
4:0
RO
0x1
num_chan:
Number of channels. Specifies the number of DMA channels. The IIO supports 
1 DMA Channel per function so this register will always read 1.
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