Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
335
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.5.2
XFERCAP
Transfer Capacity.
The Transfer Capacity specifies the minimum of the maximum DMA transfer size 
supported on all channels.
14.5.3
GENCTRL
DMA General Control.
The DMA Control register provides for general control operations.
14.5.4
INTRCTRL
The Interrupt Control register provides for control of DMA interrupts.
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
4Function:0-7
Offset:
0x1
Bit
Attr
Default
Description
7:5
RV
-
Reserved. 
4:0
RO
0x14
trans_size:
Transfer size. This field specifies the number of bytes that may be specified in 
a DMA descriptor’s Transfer Size field. This defines the maximum transfer size 
supported by IIO as a power of 2. CPU will support 1M max.
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
4Function:0-7
Offset:
0x2
Bit
Attr
Default
Description
7:1
RV
-
Reserved. 
0:0
RW
0x0
dbgen:
Debug Enable
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
4Function:0-7
Offset:
0x3
Bit
Attr
Default
Description
7:4
RV
-
Reserved. 
3:3
RW
0x0
msix_vecctrl:
Intel® Quick Data DMA ignores this bit
2:2
RO
0x0
intp:
Interrupt. This bit is set whenever the channel status bit in the Attention 
Status register is set and the Master Interrupt Enable bit is set. That is, it is 
the logical AND of Interrupt Status and Master Interrupt Enable bits of this 
register. This bit represents the legacy interrupt drive signal (when in legacy 
interrupt mode). In MSI-X mode, this bit is not used by software and is a 
don’t care.
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