Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
348
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.5.23 CHANERRMSK
Channel Error Mask Register.
14.5.24 DCACTRL
DCA Control.
14.5.25 DCA_VER
DCA Version Number Register.
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
4Function:0-7
Offset:
0xac
Bit
Attr
Default
Description
31:19
RV
-
Reserved. 
18:18
RWS (Function 0-1)
RO (Function 2-7)
0x0
mask18:
This register is a bit for bit mask for the CHANERR register
0: enable
1: disable
17:17
RWS (Function 0-1)
RO (Function 2-7)
0x0
mask17:
This register is a bit for bit mask for the CHANERR register
0: enable
1: disable
16:16
RWS
0x0
mask16:
This register is a bit for bit mask for the CHANERR register
0: enable
1: disable
15:14
RV
-
Reserved. 
13:0
RWS
0x0
mask13_0:
This register is a bit for bit mask for the CHANERR register
0: enable
1: disable
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
4Function:0-7
Offset:
0xb0
Bit
Attr
Default
Description
31:16
RV
-
Reserved. 
15:0
RW_L
0x0
target_cpu:
Specifies the APIC ID of the target CPU for Completion Writes. This field is 
RW if CHANCNT register is 1 otherwise this register is RO.
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
4Function:0-7
Offset:
0x100
Bit
Attr
Default
Description
7:4
RO
0x1
major_revision:
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