Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
346
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
17:17
RW1CS (Function 0-1)
RO (Function 2-7)
0x0
xorqerr:
The hardware sets this bit when the Q validation part of the
XOR with Galois Field Multiply Validate operation fails.
16:16
RW1CS
0x0
crc_xorp_err:
The hardware sets this bit when a CRC Test operation or XOR 
Validity operation fails or when the P validation part of the 
XOR with Galois Field Multiply Validate operation fails.
15:15
RO
0x0
unaffil_err:
Unaffiliated Error . IIO never sets this bit
14:14
RV
-
Reserved. 
13:13
RW1CS
0x0
int_cfg_err:
Interrupt Configuration Error. The DMA channel sets this bit 
indicating that the interrupt registers were not configured 
properly when the DMA channel attempted to generate an 
interrupt. E.g. interrupt address is not 0xFEE.
12:12
RW1CS
0x0
cmp_addr_err:
Completion Address Error. The DMA channel sets this bit 
indicating that the completion address register was configured 
to an illegal address or has not been configured.
11:11
RW1CS
0x0
desc_len_err:
Descriptor Length Error. The DMA channel sets this bit 
indicating that the current transfer has an illegal length field 
value. When this bit has been set, the address of the failed 
descriptor is in the Channel Status register.
10:10
RW1CS
0x0
desc_ctrl_err:
Descriptor Control Error. The DMA channel sets this bit 
indicating that the current transfer has an illegal control field 
value. When this bit has been set, the address of the failed 
descriptor is in the Channel Status register.
9:9
RW1CS
0x0
wr_data_err:
Write Data Error. The DMA channel sets this bit indicating that 
the current transfer has encountered an error while writing 
the destination data. This error could be because of an 
internal ram error in the write queue that stores the write data 
before being written to main memory. When this bit has been 
set, the address of the failed descriptor is in the Channel 
Status register.
8:8
RW1CS
0x0
rd_data_err:
Read Data Error. The DMA channel sets this bit indicating that 
the current transfer has encountered an error while accessing 
the source data. This error could be a read data that is 
received poisoned. When this bit has been set, the address of 
the failed descriptor is in the Channel Status register.
7:7
RW1CS
0x0
dma_data_parerr:
DMA Data Parity Error. The DMA channel sets this bit 
indicating that the current transfer has encountered an 
uncorrectable ECC/parity error reported by the DMA engine.
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
4Function:0-7
Offset:
0xa8
Bit
Attr
Default
Description
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