Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
405
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
26:26
RW
0x0
queued_invalidation_enable:
Software writes to this field to enable queued invalidations.0: Disable 
queued invalidations. In this case, invalidations must be performed through 
the Context Command and IOTLB Invalidation Unit registers.
1: Enable use of queued invalidations. Once enabled, all invalidations must 
be submitted through the invalidation queue and the invalidation registers 
cannot be used till the translation has been disabled. The invalidation queue 
address register must be initialized before enabling queued invalidations. 
Also software must make sure that all invalidations submitted prior via the 
register interface are all completed before enabling the queued invalidation 
interface.
Hardware reports the status of queued invalidation enable operation through 
QIES field in the Global Status register. Value returned on read of this field is 
undefined.
25:25
RW
0x0
interrupt_remapping_enable:
0: Disable Interrupt Remapping Hardware1: Enable Interrupt Remapping 
Hardware
Hardware reports the status of the interrupt-remap enable operation 
through the IRES field in the Global Status register.
Before enabling (or reenabling) Interrupt-remapping hardware through this 
field, software must:
- Setup the interrupt-remapping structures in memory
- Set the Interrupt Remap table pointer in hardware (through IRTP field).
- Perform global invalidation of IOTLB
There may be active interrupt requests in the platform when software 
updates this field. Hardware must enable or disable remapping logic only at 
deterministic transaction boundaries, so that any in-flight interrupts are 
either subject to remapping or not at all. IIO must drain any in-flight 
translated DMA read/write, MSI interrupt requests queued within the root 
complex before completing the translation enable command and reflecting 
the status of the command through the IRES field in the GSTS_REG. Value 
returned on read of this field is undefined. 
24:24
RW_V
0x0
set_interrupt_remap_table_pointer:
Software sets this field to set/update the interrupt remapping table pointer 
used by hardware. The interrupt remapping table pointer is specified 
through the Interrupt Remapping Table Address register.Hardware reports 
the status of the interrupt remapping table pointer set operation through the 
IRTPS field in the Global Status register.
The interrupt remap table pointer set operation must be performed before 
enabling or reenabling (after disabling) interrupt remapping hardware 
through the IRE field.
After an interrupt remap table pointer set operation, software must globally 
invalidate the interrupt entry cache. This is required to ensure hardware 
uses only the interrupt remapping entries referenced by the new interrupt 
remap table pointer, and not any stale cached entries.
While interrupt remapping is active, software may update the interrupt 
remapping table pointer through this field. However, to ensure valid in-flight 
interrupt requests are deterministically remapped, software must ensure 
that the structures referenced by the new interrupt remap table pointer are 
programmed to provide the same remapping results as the structures 
referenced by the previous interrupt remap table pointer. Clearing this bit 
has no effect. IIO hardware internally clears this field before the ’set’ 
operation requested by software has take effect.
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
5Function:0
Offset:
0x18, 0x1018
Bit
Attr
Default
Description
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