Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
407
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.7.6
VTD[0:1]_ROOTENTRYADD
Intel
®
VT-d Root Entry Table Address.
14.7.7
VTD[0:1]_CTXCMD
Intel
®
VT-d Context Command.
24:24
RO_V
0x0
interrupt_remapping_table_pointer_status:
This field indicates the status of the interrupt remapping table pointer in 
hardware. This field is cleared by hardware when software sets the SIRTP 
field in the Global Command register. This field is set by hardware when 
hardware completes the set interrupt remap table pointer operation using 
the value provided in the Interrupt Remapping Table Address register. 
23:23
RO_V
0x0
cfis:
Compatibility Format Interrupt Status
The value reported in this field is applicable only when interrupt-remapping 
is enabled and Legacy interrupt mode is active.
0: Compatibility format interrupts are blocked.
1: Compatibility format interrupts are processed as pass-through (bypassing 
interrupt remapping).
22:0
RV
-
Reserved.
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
5Function:0
Offset:
0x1c, 0x101c
Bit
Attr
Default
Description
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
5Function:0
Offset:
0x20, 0x1020
Bit
Attr
Default
Description
63:12
RW
0x0
root_entry_table_base_address:
4K aligned base address for the root entry table. Software specifies the base 
address of the root-entry table through this register, and enables it in 
hardware through the SRTP field in the Global Command register. Reads of 
this register returns value that was last programmed to it. 
11:0
RV
-
Reserved.
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