Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
433
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.8.23 ERRPINCTL
This register provides the option to configure an error pin to either as a special purpose 
error pin which is asserted based on the detected error severity, or as a general 
purpose output which is asserted based on the value in the ERRPINDAT. The assertion 
of the error pins can also be completely disabled by this register.
14.8.24 ERRPINSTS
This register reflects the state of the error pin assertion. The status bit of the 
corresponding error pin is set upon the deassertion to assertion transition of the error 
pin. This bit is cleared by the software with writing 1 to the corresponding bit.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:2
Offset:
0xa4
Bit
Attr
Default
Description
31:6
RV
-
Reserved.
5:4
RW
0x0
pin2:
11: Reserved.
10: Assert Error Pin when error severity 2 is set in the system event status 
reg.
01: Assert and Deassert Error pin according to error pin data register.
00: Disable Error pin assertion
3:2
RW
0x0
pin1:
11: Reserved.
10: Assert Error Pin when error severity 1 is set in the system event status 
reg.
01: Assert and Deassert Error pin according to error pin data register.
00: Disable Error pin assertion
1:0
RW
0x0
pin0:
11: Reserved.
10: Assert Error Pin when error severity 0 is set in the system event status 
reg.
01: Assert and Deassert Error pin according to error pin data register.
00: Disable Error pin assertion
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5
Function:
2
Offset:
0xa8
Bit
Attr
Default
Description
31:3
RV
-
Reserved1:
Reserved.
2:2
RW1CS
0x0
pin2:
This bit is set upon the transition of deassertion to assertion of the Error pin. 
Software write 1 to clear the status. Hardware will only set this bit when the 
corresponding ERRPINCTL field is set to 10b.
1:1
RW1CS
0x0
pin1:
This bit is set upon the transition of deassertion to assertion of the Error pin. 
Software write 1 to clear the status. Hardware will only set this bit when the 
corresponding ERRPINCTL field is set to 10b.
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