Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
478
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.9.4
PCISTS
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:4
Offset:
0x6
Bit
Attr
Default
Description
15:15
RO_V
0x0
dpe:
This bit is set when the device receives a packet on the primary side with an 
uncorrectable data error (including a packet with poison bit set) or an 
uncorrectable address/control parity error. The setting of this bit is 
regardless of the Parity Error Response bit (PERRE) in the PCICMD register. 
R2PCIe will never set this bit.
14:14
RO
0x0
sse:
Hardwired to 0.
13:13
RO
0x0
rma:
Hardwired to 0.
12:12
RO
0x0
rta:
Hardwired to 0.
11:11
RW1C
0x0
sta:
Hardwired to 0.
10:9
RO
0x0
devselt:
Hardwired to 0.
8:8
RO
0x0
medierr:
Hardwired to 0.
7:7
RO
0x0
fb2bcap:
Hardwired to 0.
6:6
RV
-
Reserved. 
5:5
RO
0x0
sixtysixmhzcap:
Hardwired to 0.
4:4
RO
0x1
capl:
This bit indicates the presence of a capabilities list structure.
3:3
RO
0x0
intxst:
Hardwired to 0.
2:0
RV
-
Reserved. 
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