Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
490
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.10.1 INDEX
The Index Register will select which indirect register appears in the window register to 
be manipulated by software. Software will program this register to select the desired 
APIC internal register.
14.10.2 WINDOW
14.10.3 EOI
14.10.4 Device 5 Function 4 Window 0
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
5Function:4
Offset:
0x0
Bit
Attr
Default
Description
7:0
RW_L
0x0
idx:
Indirect register to access.
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
5Function:4
Offset:
0x10
Bit
Attr
Default
Description
31:0
RW_LV
0x0
window_reg:
Data to be written to the indirect registers on writes, and location of read 
data from the indirect register on reads.
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
5Function:4
Offset:
0x40
Bit
Attr
Default
Description
7:0
RW_L
0x0
eoi_reg:
The EOI register is present to provide a mechanism to efficiently convert level 
interrupts to edge triggered MSI interrupts. When a write is issued to this 
register, the I/O(x)APIC will check the lower 8 bits written to this register, 
and compare it with the vector field for each entry in the I/O Redirection 
Table. When a match is found, the Remote_IRR bit for that I/O Redirection 
Entry will be cleared. Note that if multiple I/O Redirection entries, for any 
reason, assign the same vector, each of those entries will have the 
Remote_IRR bit reset to ’0’. This will cause the corresponding I/OxAPIC 
entries to resample their level interrupt inputs and if they are still asserted, 
cause more MSI interrupts (if unmasked) which will again set the 
Remote_IRR bit.
Register name
Offset
Size
APICID__WINDOW
0x0
32
VER__WINDOW
0x1
32
ARBID__WINDOW
0x2
32
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