Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
492
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.10.4.1 APICID__WINDOW
This register uniquely identifies an APIC in the system. This register is not used by 
OS’es anymore and is still implemented in hardware because of FUD.
14.10.4.2 VER__WINDOW
This register uniquely identifies an APIC in the system. This register is not used by 
OSes anymore and is still implemented in hardware because of FUD. 
RTL21__WINDOW
0x3a
32
RTH21__WINDOW
0x3b
32
RTL22__WINDOW
0x3c
32
RTH22__WINDOW
0x3d
32
RTL23__WINDOW
0x3e
32
RTH23__WINDOW
0x3f
32
Register name
Offset
Size
Type:
MEM
PortID:
N/A
Bus:
0
Device:
5Function:4
Offset:
0x0
Bit
Attr
Default
Description
31:28
RV
-
Reserved.
27:24
RW
0x0
apicid:
Allows for up to 16 unique APIC IDs in the system.
23:0
RV
-
Reserved.
Type:
MEM
PortID:
N/A
Bus:
0
Device:
5Function:4
Offset:
0x1
Bit
Attr
Default
Description
31:24
RV
-
Reserved.
23:16
RO
0x17
max:
This is the entry number of the highest entry in the redirection table. It is 
equal to the number of interrupt inputs minus one. This field is hardwired to 
17h to indicate 24 interrupts.
15:15
RO
0x0
prq:
This bit is set to 0 to indicate that this version of the I/OxAPIC does not 
implement the IRQ Assertion register and does not allow PCI devices to write 
to it to cause interrupts. 
14:8
RV
-
Reserved.
7:0
RO
0x20
vs:
This identifies the implementation version. This field is hardwired to 20h 
indicate this is an I/OxAPIC.
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