Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
495
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.10.4.6 RTH[0:23]__WINDOW
10:8
RW
0x0
delm:
This field specifies how the APICs listed in the destination field should act 
upon reception of the interrupt. Certain Delivery Modes will only operate as 
intended when used in conjunction with a specific trigger mode. The 
encodings are:000 - Fixed: Trigger Mode can be edge or level. Examine TM 
bit to determine.
001 - Lowest Priority: Trigger Mode can be edge or level. Examine TM bit to 
determine.
010 - SMI/PMI: Trigger mode is always edge and TM bit is ignored.
011 - Reserved
100 - NMI. Trigger mode is always edge and TM bit is ignored.
101 - INIT. Trigger mode is always edge and TM bit is ignored.
110 - Reserved
111 - ExtINT. Trigger mode is always edge and TM bit is ignored. 
7:0
RW
0x0
vct:
This field contains the interrupt vector for this interrupt 
Type:
MEM
PortID:
N/A
Bus:
0
Device:
5Function:4
Offset:
0x11, 0x13, 0x15, 0x17, 0x19, 0x1b, 0x1d, 0x1f,
0x21, 0x23, 0x25, 0x27, 0x29, 0x2b, 0x2d, 0x2f,
0x31, 0x33, 0x35, 0x37, 0x39, 0x3b, 0x3d, 0x3f
Bit
Attr
Default
Description
31:24
RW
0x0
did:
They are bits [19:12] of the MSI address. 
23:16
RW
0x0
edid:
These bits become bits [11:4] of the MSI address.
15:0
RV
-
Reserved.
Type:
MEM
PortID:
N/A
Bus:
0
Device:
5Function:4
Offset:
0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e, 
0x20, 0x22, 0x24, 0x26, 0x28, 0x2a,  0x2c, 0x2e,
0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e
Bit
Attr
Default
Description
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