Intel E7-8891 v2 CM8063601377422 User Manual

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Reliability, Availability, Serviceability, and Manageability
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
Fatal Errors (Severity 2 Error)
Fatal errors are uncorrectable error conditions which render the IO module hardware 
unreliable. For fatal error, inband reporting to the CPU is still possible. A reset may be 
required to return to reliable operation.
Inband Error Reporting
Inband error reporting signals the system of a detected error via inband cycles.
IIO Viral
Viral containment is now supported in the IIO. The logic implemented in the IIO is part 
of a global viral mechanism.
Error Counters
This feature allows the system management controller to monitor the component’s 
health by periodically reporting the correctable error count. 
At the high bit rate of Gen. 3 PCIe, a higher bit error rate (BER) is possible due to the 
thermal fluctuations caused by ASPM. To deal with this issue, it is necessary to monitor 
bit errors per unit time (CRC errors during a sliding window). If the number of errors 
per unit time exceeds a programmable threshold, the link will need to be placed in 
Recovery to recalibrate the equalization. See the PCI Express 3.0 specification for more 
PCI Express RAS
PCI Express Base Specification, Revision 3.0 defines a standard set of error reporting 
mechanisms and the IO module supports them all including the error poisoning and 
Advanced Error Reporting. Any exceptions are called out where appropriate.
PCI Express Link CRC and Retry
PCIe supports link CRC and link level retry for CRC error.  Refer to PCIe Base 
specification 3.0 for the details.
Link Retraining and Recovery
PCIe interface provides a mechanism to recover from a failed link. PCIe link is capable 
of operating in different link width. The IO module will support PCIe port operation in 
x16, x8, x4, x2, and x1. In case of a persistent link failure, the PCIe link can fall back to 
a smaller link width in attempt to recover from the error. This mechanism enables 
continuation of system operation in case of PCIe link failures. Refer to PCIe Base 
specification 3.0 for further details.
PCI Express Error Reporting Mechanism
The IO module supports the standard and advanced PCIe error reporting for its PCIe 
ports. Since the IO module belongs to root complex, its PCIe ports are implemented 
as root ports. Refer to PCIe Base specification 3.0 for the details of PCIe error 
reporting. The following sections highlight the important aspects of PCIe error 
reporting mechanism.
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