Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Processor Uncore Configuration Registers
92
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13.2.1.2
MCMTR
MC Memory Technology
19:16
RO
0x1
Capability Version (capability_version):
PCI Express Capability is Compliant with Version 1.0 of the PCI Express 
Spec.
Note:
This capability structure is not compliant with Versions beyond 1.0, since 
they require additional capability registers to be reserved. The only purpose 
for this capability structure is to make enhanced configuration space 
available. Minimizing the size of this structure is accomplished by reporting 
version 1.0 compliancy and reporting that this is an integrated root port 
device. As such, only three Dwords of configuration space are required for 
this structure.
15:8
RO
0x0
Next Capability Pointer (next_ptr):
Pointer to the next capability. Set to 0 to indicate there are no more 
capability structures.
7:0
RO
0x10
Capability ID (capability_id):
Provides the PCI Express capability ID assigned by PCI-SIG.
Type:
CFG
PortID:
N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0x40
Bit
Attr
Default
Description
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0x7c
Bit
Attr
Default
Description
31:20
RV
-
Reserved.
19:16
RW_LB
0x0
CHN_DISABLE (chn_disable):
Channel disable control. When set, the corresponding channel is disabled. 
Note: Message Channel may not work if all channels are set to disable in 
this field.
15:14
RV
-
Reserved:
13:12
RW_LB
0x0
IMC_MODE (imc_mode):
Memory mode:
00: Reserved
01: Reserved
10: VMSE 1:1 Subchannel Lockstep Mode
11: VMSE 2:1 Performance Mode
Note that in EX mode, both MC0 and MC1 need set this field to the 
correspondent VMSE mode. Not doing that might cause Msg Channel access 
to hang.
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