Intel J1850 FH8065301455200 User Manual

Intel

Product codes

FH8065301455200

Datasheet

1005

PCU - Power Management Controller (PMC)

19.7

PCU iLB PMC I/O Registers

Table 146.

Summary of PCU iLB PMC I/O Registers—ACPI_BASE_ADDRESS

Offset

Size

Register ID—Description

Default

Value

0h

4

“PM1_STS_EN - Power Management 1 Status and enable (PM1_STS_EN)—Offset

0h” on page 1006

00000000h

4h

4

“PM1_CNT - Power Management 1 Control (PM1_CNT)—Offset 4h” on page 1008

00000000h

8h

4

“PM1_TMR - Power Management 1 Timer (PM1_TMR)—Offset 8h” on page 1009

00000000h

20h

4

“GPE0a_STS - General Purpose Event 0 Status (GPE0a_STS)—Offset 20h” on

00000000h

28h

4

“GPE0a_EN - General Purpose Event 0 Enables (GPE0a_EN)—Offset 28h” on

00000000h

30h

4

“SMI_EN - SMI Control and Enable (SMI_EN)—Offset 30h” on page 1014

00000002h

34h

4

“SMI_STS - SMI Status Register (SMI_STS)—Offset 34h” on page 1015

00000000h

38h

4

“ALT_GPIO_SMI - Alternate GPIO SMI Status and Enable Register.

(ALT_GPIO_SMI)—Offset 38h” on page 1017

00000000h

3Ch

4

“UPRWC - USB Per-Port Registers Write Control (UPRWC)—Offset 3Ch” on

00000000h

40h

4

“GPE_CTRL - General Purpose Event Control (GPE_CTRL)—Offset 40h” on

00000000h

50h

4

“PM2A_CNT_BLK - PM2a Control Block (PM2A_CNT_BLK)—Offset 50h” on

00000000h

60h

4

“TCO_RLD: TCO Reload Register (TCO_RLD)—Offset 60h” on page 1020

00000000h

64h

4

“TCO_STS: TCO Timer Status (TCO_STS)—Offset 64h” on page 1021

00000000h

68h

4

“TCO1_CNT: TCO Timer Control (TCO1_CNT)—Offset 68h” on page 1021

00000000h

70h

4

“TCO_TMR: TCO Timer Register (TCO_TMR)—Offset 70h” on page 1022

00040000h