Intel J1850 FH8065301455200 User Manual
Product codes
FH8065301455200
Datasheet
1037
PCU – Serial Peripheral Interface (SPI)
20.2.9.2
Serial Flash Device Package Recommendations
It is highly recommended that the common footprint usage model be supported. An
example of how this can be accomplished is as follows:
example of how this can be accomplished is as follows:
•
The recommended pinout for 8-pin serial Flash devices is used (refer to
).
•
The 8-pin device is supported in either an 8-contact VDFPN (6x5 mm MLP) package
or an 8-contact WSON (5x6 mm) package. These packages can fit into a socket
that is land pattern compatible with the wide body SO8 package.
or an 8-contact WSON (5x6 mm) package. These packages can fit into a socket
that is land pattern compatible with the wide body SO8 package.
•
The 8-pin device is supported in the SO8 (150 mil) and in the wide-body SO8 (200
mil) packages.
mil) packages.
•
The 16-pin device is supported in the SO16 (300 mil) package.
20.3
Use
20.3.1
Hardware vs. Software Sequencing
Hardware and Software sequencing are the two methods the processor uses to
communicate with the Flash via programming registers for each of the three masters.
communicate with the Flash via programming registers for each of the three masters.
20.3.1.1
Hardware Sequencing
Hardware sequencing has a predefined list of opcodes, see
with only the erase opcode being programmable. This mode is only available if the
descriptor is present and valid. Security Engine firmware must use HW sequencing;
thus, BIOS must properly set up the processor to account for this. The Host VSCC
registers and VSCC Table have to be correctly configured for BIOS and Security Engine
have read/write access to SPI.
descriptor is present and valid. Security Engine firmware must use HW sequencing;
thus, BIOS must properly set up the processor to account for this. The Host VSCC
registers and VSCC Table have to be correctly configured for BIOS and Security Engine
have read/write access to SPI.
20.3.1.2
Software Sequencing
All commands other than the standard (memory) reads must be programmed by the
software in the Software Sequencing Control, Flash Address, Flash Data, and Opcode
configuration registers. Software must issue either Read ID or Read JEDEC ID, or a
combination of the two to determine what Flash component is attached. Based on the
Read ID, software can determine the appropriate Opcode instructions sets to set in the
program registers and at what SPI frequency to run the command.
software in the Software Sequencing Control, Flash Address, Flash Data, and Opcode
configuration registers. Software must issue either Read ID or Read JEDEC ID, or a
combination of the two to determine what Flash component is attached. Based on the
Read ID, software can determine the appropriate Opcode instructions sets to set in the
program registers and at what SPI frequency to run the command.
Software must program the Flash Linear Address for all commands, even for those
commands that do not require address such as the Read ID or Read Status. This is
because the SPI controller uses the address to determine which chip select to use.
commands that do not require address such as the Read ID or Read Status. This is
because the SPI controller uses the address to determine which chip select to use.
The opcode type and data byte count fields determine how many clocks to run before
deasserting the chip enable. The Flash data is always shifted in for the number of bytes
specified and the Flash Data out is always shifted out for the number of data bytes
specified. Note that the hardware restricts the burst lengths that are allowed.
deasserting the chip enable. The Flash data is always shifted in for the number of bytes
specified and the Flash Data out is always shifted out for the number of data bytes
specified. Note that the hardware restricts the burst lengths that are allowed.