Intel J1850 FH8065301455200 User Manual
Product codes
FH8065301455200
Datasheet
1121
PCU – System Management Bus (SMBus)
22.7.10
Auxiliary Control (SMB_Mem_AUXC)—Offset Dh
Access Method
Default: 00h
22.7.11
SMBUS_PIN_CTL Register (SMB_Mem_SMBC)—Offset Fh
Software bus accesses register
Access Method
Default: 07h
Type: Memory Mapped I/O Register
(Size: 8 bits)
SMB_Mem_AUXC: [MBARL] + Dh
MBARL Type: PCI Configuration Register (Size: 32 bits)
MBARL Reference: [B:0, D:31, F:3] + 10h
MBARL Reference: [B:0, D:31, F:3] + 10h
7
4
0
0
0
0
0
0
0
0
0
RS
V1
E32B
AAC
Bit
Range
Default &
Access
Description
7:2
000000b
RO
Reserved (RSV1): Reserved
1
0b
RW
E32B: Enable 32-byte Buffer (E32B) - When set, the Host Block Data register is a
pointer into a 32-byte buffer, as opposed to a single register. This enables the block
commands to transfer or receive up to 32-bytes before the controller generates an
interrupt
0
0b
RW/O
AAC: Automatically Append CRC (AAC) - When set, the SMBus controller will
automatically append the CRC. This bit must not be changed during SM Bus
transactions, or undetermined behavior will result. It should be programmed only once
during the lifetime of the function.
Type: Memory Mapped I/O Register
(Size: 8 bits)
SMB_Mem_SMBC: [MBARL] + Fh
MBARL Type: PCI Configuration Register (Size: 32 bits)
MBARL Reference: [B:0, D:31, F:3] + 10h
MBARL Reference: [B:0, D:31, F:3] + 10h
7
4
0
0
0
0
0
0
1
1
1
RS
V1
SMB
C
LK
C
T
L
SMBDA
T
SMB
C
LK
Bit
Range
Default &
Access
Description
7:3
00000b
RO
Reserved (RSV1): Reserved