Intel J1850 FH8065301455200 User Manual

1122

Datasheet

All bits in this register are implemented in the 64 kHz clock domain. Therefore, 

software must poll the register until a write takes effect before assuming that a write 

has completed internally

Default: 00h

All bits in this register are implemented in a slow (64khz) clock domain. Therefore, 

software must poll the register until a write takes effect before assuming that a write 

has completed internally. Also, software must confirm the prior written value before 

writing to the register again.

2

1b

RW

SMBCLKCTL: This Read/Write bit has a default of 1. 0 = SMBus controller will drive the 

SMB_CLK pin low, independent of what the other SMB logic would otherwise indicate for 

the SMB_CLK pin. 1 = The SMB_CLK pin is Not overdriven low. The other SMBus logic 

controls the state of the pin.

1

1b

RO

SMBDAT: This pin returns the value on the SMB_DATA pin. It will be 1 to indicate high, 

0 to indicate low. This allows software to read the current state of the pin.

0

1b

RO

SMBCLK: This pin returns the value on the SMB_CLK pin. It will be 1 to indicate high, 0 

to indicate low. This allows software to read the current state of the pin.

Type: Memory Mapped I/O Register

(Size: 8 bits)

MBARL Type: PCI Configuration Register (Size: 32 bits)
MBARL Reference: [B:0, D:31, F:3] + 10h

7

4

0

0

0

0

0

0

0

0

0

RSV1

HNS

T

7:1

0000000b

RO

Reserved (RSV1): Reserved

0

0b

RW

HNST: HOST_NOTIFY_STS: The SMBus controller sets this bit to a 1 when it has 

completely received a successful Host Notify Command on the SMBus pins. Software 

reads this bit to determine that the source of the interrupt or SMI# was the reception of 

the Host Notify Command. Software clears this bit after reading any information needed 

from the Notify address and data registers by writing a 1 to this bit. Note that the 

SMBus controller will allow the Notify Address and Data registers to be over-written 

once this bit has been cleared. When this bit is 1, the SMBus controller will NACK the 

first byte (host address) of any new 'Host Notify' commands on the SMBus. Writing a 0 

to this bit has no effect.