Intel J1850 FH8065301455200 User Manual
Product codes
FH8065301455200
Datasheet
1251
PCU - iLB - IO APIC
30.5
PCU iLB IO APIC Memory Mapped I/O Registers
30.5.1
IDX (IOAPIC_IDX)—Offset FEC00000h
Index Register
Access Method
Default: 00h
30.5.2
WDW (IOAPIC_WDW)—Offset FEC00010h
Window Register
Access Method
Default: 00000000h
Table 187.
Summary of PCU iLB I/O APIC Memory Mapped I/O Registers
Offset
Size
Register ID—Description
Default
Value
FEC00000h
1
00h
FEC00010h
4
00000000h
FEC00040h
4
00000000h
Type: Memory Mapped I/O Register
(Size: 8 bits)
IOAPIC_IDX: FEC00000h
7
4
0
0
0
0
0
0
0
0
0
IDX
Bit
Range
Default &
Access
Description
7:0
0h
RW
IDX: This 8-bit register selects which indirect register appears in the window register to
be manipulated by software. Software will program this register to select the desired
APIC internal register.
Type: Memory Mapped I/O Register
(Size: 32 bits)
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
WD
W
Bit
Range
Default &
Access
Description
31:0
0h
RW
WDW: This 32-bit register specifies the data to be read or written to the register
pointed to by the IDX register. This register can be accessed only in DW quantities.