Intel J1850 FH8065301455200 User Manual
Product codes
FH8065301455200
Datasheet
1253
PCU – iLB – 8259 Programmable Interrupt Controllers (PIC)
31
PCU – iLB – 8259
Programmable Interrupt
Controllers (PIC)
The processor provides an ISA-compatible programmable interrupt controller (PIC) that
incorporates the functionality of two, cascaded 8259 interrupt controllers.
incorporates the functionality of two, cascaded 8259 interrupt controllers.
31.1
Features
In addition to providing support for ISA compatible interrupts, this interrupt controller
can also support PCI-based interrupts (PIRQs) by mapping the PCI interrupt onto a
compatible ISA interrupt line. Each 8259 controller supports eight interrupts, numbered
0–7.
can also support PCI-based interrupts (PIRQs) by mapping the PCI interrupt onto a
compatible ISA interrupt line. Each 8259 controller supports eight interrupts, numbered
0–7.
shows how the controllers are connected.
Note:
The processor does not implement any external PIRQ# signals. The PIRQs referred to
in this chapter originate from the interrupt routing unit.
in this chapter originate from the interrupt routing unit.
I
O
I
O
I
O
I
O
I
O
I
O
I
O
O
Platform Control Unit
UAR
T
LPC
GP
IO
IO
RT
C
C
HPET
82
59
59
AP
IC
IC
82
54
54
SMB
iLB
SP
I
I
PMC
Table 188. Interrupt Controller Connections (Sheet 1 of 2)
8259
8259
Input
Connected Pin / Function
Master
0
Internal Timer / Counter 0 output or HPET #0; determined by GCFG.LRE register bit
1
IRQ1 using SERIRQ, Keyboard Emulation
2
Slave controller INTR output
3
IRQ3 via SERIRQ, PIRQx or PCU UART 1
4
IRQ4 via SERIRQ or PIRQx
5
IRQ5 via SERIRQ or PIRQx
6
IRQ6 via SERIRQ or PIRQx
7
IRQ7 via SERIRQ or PIRQx