Intel J1850 FH8065301455200 User Manual
Product codes
FH8065301455200
PCU – iLB – 8259 Programmable Interrupt Controllers (PIC)
1260
Datasheet
31.1.6
Masking Interrupts
31.1.6.1
Masking on an Individual Interrupt Request
Each interrupt request can be masked individually by the Interrupt Mask Register
(IMR). This register is programmed through OCW1. Each bit in the IMR masks one
interrupt channel. Masking IRQ2 on the master controller masks all requests for service
from the slave controller.
(IMR). This register is programmed through OCW1. Each bit in the IMR masks one
interrupt channel. Masking IRQ2 on the master controller masks all requests for service
from the slave controller.
31.1.6.2
Special Mask Mode
Some applications may require an interrupt service routine to dynamically alter the
system priority structure during its execution under software control. For example, the
routine may wish to inhibit lower priority requests for a portion of its execution but
enable some of them for another portion.
system priority structure during its execution under software control. For example, the
routine may wish to inhibit lower priority requests for a portion of its execution but
enable some of them for another portion.
The special mask mode enables all interrupts not masked by a bit set in the Mask
register. Normally, when an interrupt service routine acknowledges an interrupt without
issuing an EOI to clear the ISR bit, the interrupt controller inhibits all lower priority
requests. In the special mask mode, any interrupts may be selectively enabled by
loading the Mask Register with the appropriate pattern.
register. Normally, when an interrupt service routine acknowledges an interrupt without
issuing an EOI to clear the ISR bit, the interrupt controller inhibits all lower priority
requests. In the special mask mode, any interrupts may be selectively enabled by
loading the Mask Register with the appropriate pattern.
The special mask mode is set by OCW3.ESMM=1b & OCW3.SMM=1b, and cleared
where OCW3.ESMM=1b & OCW3.SMM=0b.
where OCW3.ESMM=1b & OCW3.SMM=0b.
31.2
IO Mapped Registers
The interrupt controller registers are located at 20h and 21h for the master controller
(IRQ0 - 7), and at A0h and A1h for the slave controller (IRQ8 - 13). These registers
have multiple functions, depending upon the data written to them.
is a
description of the different register possibilities for each address.
Note:
The register descriptions after
represent one register possibility.
Table 191.
I/O Registers Alias Locations (Sheet 1 of 2)
Registers
Original I/O Location
Alias I/O Locations
MICW1
MOCW2
MOCW3
20h
24h
28h
2Ch
30h
34h
38h
3Ch