Intel J1850 FH8065301455200 User Manual
Product codes
FH8065301455200
PCU - iLB - 8259 Programmable Interrupt Controllers (PIC)
1262
Datasheet
31.3
PCU iLB 8259 Interrupt Controller (PIC) I/O Registers
31.3.1
MICW1—Offset 20h
Master Initialization Command Word 1.A write to Initialization Command Word 1 starts
the interrupt controller initialization sequence, during which the following occurs: * The
Interrupt Mask register is cleared. * IRQ7 input is assigned priority 7. * The slave mode
address is set to 7. * Special Mask Mode is cleared and Status Read is set to IRR. Once
this write occurs, the controller expects writes to ICW2, ICW3, and ICW4 to complete
the initialization sequence.
Access Method
Default: 00h
Table 192.
Summary of PCU iLB 8259 Interrupt Controller (PIC) I/O Registers
Offset
Size
Register ID—Description
Default
Value
20h
1
00h
21h
1
00h
24h
1
20h
25h
1
00h
28h
1
22h
29h
1
01h
2Dh
1
00h
A0h
1
00h
A1h
1
00h
A4h
1
20h
A5h
1
00h
A8h
1
22h
A9h
1
01h
ADh
1
00h
4D0h
1
00h
4D1h
1
00h
Type: I/O Register
(Size: 8 bits)
MICW1: 20h
7
4
0
0
0
0
0
0
0
0
0
MC
S85
ICWO
CWS
E
L
LT
IM
ADI
SNG
L
IC4
Bit
Range
Default &
Access
Description
7:5
X
WO
MCS85: These bits are MCS-85 specific, and not needed. Should be programmed to 000