Intel J1850 FH8065301455200 User Manual

16

Datasheet

ACPI

Advanced Configuration and Power Interface

Cold Reset

Full reset is when PWROK is de-asserted and all system rails except VCCRTC are powered 

down

CRT

Cathode Ray Tube

CRU

Clock Reset Unit

DP

Display Port

DTS

Digital Thermal Sensor

EIOB

Electronic In/Out Board

EMI

Electro Magnetic Interference

eDP

embedded Display Port

HDMI

High Definition Multimedia Interface. HDMI supports standard, enhanced, or high-definition 

video, plus multi-channel digital audio on a single cable. HDMI transmits all Advanced 

Television Systems Committee (ATSC) HDTV standards and supports 8-channel digital audio, 

with bandwidth to spare for future requirements and enhancements (additional details 

available at 

IGD

Internal Graphics Unit

Intel

®

 TXE

Intel

®

 Trusted Execution Engine

LCD

Liquid Crystal Display

MPEG

Moving Picture Experts Group

MSI

Message Signaled Interrupt. MSI is a transaction initiated outside the host, conveying 

interrupt information to the receiving agent through the same path that normally carries read 

and write commands.

MSR

Model Specific Register, as the name implies, is model-specific and may change from 

processor model number (n) to processor model number (n+1). An MSR is accessed by setting 

ECX to the register number and executing either the RDMSR or WRMSR instruction. The 

RDMSR instruction will place the 64 bits of the MSR in the EDX: EAX register pair. The WRMSR 

writes the contents of the EDX: EAX register pair into the MSR.

PCIe*

PCI Express* (PCIe*) is a high-speed serial interface. The PCIe* configuration is software-

compatible with the existing PCI specifications.

PWM

Pulse Width Modulation

Rank

A unit of DRAM corresponding to the set of SDRAM devices that are accessed in parallel for a 

given transaction. For a 64-bit wide data bus using 8-bit (x8) wide SDRAM devices, a rank 

would be eight devices. Multiple ranks can be added to increase capacity without widening the 

data bus, at the cost of additional electrical loading.

SCI

System Control Interrupt. SCI is used in the ACPI protocol.

SDRAM

Synchronous Dynamic Random Access Memory 

SERR

System Error. SERR is an indication that an unrecoverable error has occurred on an I/O bus.

SMC

System Management Controller or External Controller refers to a separate system 

management controller that handles reset sequences, sleep state transitions, and other 

system management tasks.

SMI

System Management Interrupt is used to indicate any of several system conditions (such as 

thermal sensor events, throttling activated, access to System Management RAM, chassis open, 

or other system state related activity).

TMDS

Transition-Minimized Differential Signaling. TMDS is a serial signaling interface used in DVI 

and HDMI to send visual data to a display. TMDS is based on low-voltage differential signaling 

with 8/10b encoding for DC balancing.

VCO

Voltage Controlled Oscillator

Warm Reset

Warm reset is a reset of the Processor without removing power (internal only reset for 

Processors).