Intel J1850 FH8065301455200 User Manual

24

Datasheet

This chapter describes the states of each signal before, during, and directly after reset. 
Additionally, Some signals have internal pull-up/pull-down termination resistors; the 
values are also provided. All signals with the “†” symbol are multiplexed and may not 
be available without configuration. See 

.

V1P05S

1.05 V rail. On in S0 only.

V1P0A

1.0 V rail. On in S0 through S4/5.

V1P0S

1.0 V rail. On in S0 only.

V1P0Sx

1.0 V rail. On in S0 only.

V1P24A

1.24 V rail. On in S0 through S4/5.

V1P24S

1.24 V rail. On in S0 only.

V1P24Sx

1.24 V rail. On in S0 only.

V1P35U

1.35 V rail. On in S0 through S3.

V1P8A

1.8 V rail. On in S0 through S4/5.

V1P35S

1.35 V rail. On in S0 

V1P8S

1.8 V rail. On in S0 only.

V3P3A

3.3 V rail. On in S0 through S4/5.

VAUD

1.5 V rail for HD Audio. On in S0 only.

VCC

Variable core rail. On in S0 only.

VLPC

1.8 or 3.3 V rail for LPC. On in S0 only.

VNN

Variable rail. On in S0 only.

VPCIESATA

1.0 V rail for PCIe* and SATA. On in S0 only.

VRTC

RTC voltage rail. On in S0 through G3.

VSDIO

1.8 or 3.3 V rail for SD3. On in S0 only.

VSFR

1.35 V rail for internal PLLs. On in S0 only.

VUSB2

3.3 V rail. On in S0 through S4/5.

High-Z

The processor places this output in a high-impedance state. For inputs, external drivers are 

not expected.

Do Not Care

The state of the input (driven or tri-stated) does not affect the processor. For outputs, it is 

assumed that the output buffer is in a high-impedance state.

V

OH

The processor drives this signal high with a termination of 50 Ω.

V

OL

The processor drives this signal low with a termination of 50 Ω.

Unknown

The Processor drives or expects an indeterminate value.

V

IH

The processor expects/requires the signal to be driven high.

V

IL

The processor expects/requires the signal to be driven low.