Intel J1850 FH8065301455200 User Manual
Product codes
FH8065301455200
Physical Interfaces
26
Datasheet
2.3
PCI Express* 2.0 Interface Signals
See
for more details.
2.4
USB 2.0 Host (EHCI/xHCI) Interface Signals
See
DRAM1_DQSP[7:0]
I/O
-
V1P35U
Off
High-Z
High-Z
High-Z
DRAM1_DQSN[7:0]
I/O
-
V1P35U
Off
High-Z
High-Z
High-Z
DRAM_VDD_S4_PWROK
I
-
V1P35U
V
IL
V
IH
Unknown
V
IH
DRAM_CORE_PWROK
I
-
V1P35U
V
IL
V
IL
Unknown
V
IH
DRAM_VREF
I
-
V1P35U
DRAM_RCOMP[2:0]
-
-
V1P35U
Table 4.
DDR3L System Memory Signals (Sheet 2 of 2)
Default Buffer State
Signal Name
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
Table 5.
PCI Express* 2.0 Interface Signals
Default Buffer State
Signal Name
Dir
Term
()
Plat.
Power
S4/S5
S3
Reset
Enter S0
PCIE_TXP[3:0]
O
50
VPCIESATA
Off
Off
V
OL
V
OL
PCIE_TXN[3:0]
O
50
VPCIESATA
Off
Off
V
OL
V
OL
PCIE_RXP[3:0]
I
50
VPCIESATA
Off
Off
High-Z
High-Z
PCIE_RXN[3:0]
I
50
VPCIESATA
Off
Off
High-Z
High-Z
PCIE_CLKP[3:0]
O
-
V1P0S
Off
Off
Running/
V
IL
Running/
V
IL
PCIE_CLKN[3:0]
O
-
V1P0S
Off
Off
Running/
V
IL
Running/
V
IL
PCIE_CLKREQ[3:0]#†
I
20k(H)
V1P8S
Off
Off
Pull_up
Pull_up
PCIE_RCOMP_P/N
-
-
NOTE: All signals with the “†” symbol are multiplexed and may not be available without configuration.
Default Buffer State
Signal Name
Dir
Term
()
Plat.
Power
S4/S5
S3
Reset
Enter S0
USB_DN[3:0]
I/O
-
VUSB2
USB_DP[3:0]
I/O
-
VUSB2
USB_OC[1:0]#†
I
20k(H)
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up