Intel J1850 FH8065301455200 User Manual
Product codes
FH8065301455200
Datasheet
31
Physical Interfaces
2.12
SPCU – iLB – Real Time Clock (RTC) Interface
Signals
See
2.13
PCU – iLB – Low Pin Count (LPC) Bridge Interface
Signals
See
for more details.
Default Buffer State
Signal Name
Dir
Term
()
Plat.
Power
S4/S5
S3
Reset
Enter S0
ILB_RTC_X1
I
-
VRTC
Running
Running
Running
Running
ILB_RTC_X2
O
-
VRTC
Running
Running
Running
Running
ILB_RTC_RST#
I
-
VRTC
V
IH
V
IH
V
IH
V
IH
ILB_RTC_TEST#
I
-
VRTC
V
IH
V
IH
V
IH
V
IH
ILB_RTC_EXTPAD
O
-
VRTC
Default Buffer State
Signal Name
Dir
Term
()
Plat.
Power
S4/S5
S3
Reset
Enter S0
ILB_LPC_AD[3:0]†
I/O
20k(H)
VLPC
Off
Off
Pull-up
Running
ILB_LPC_FRAME#†
I/O
20k(H)
VLPC
Off
Off
V
OH
Running
ILB_LPC_SERIRQ†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Running
ILB_LPC_CLKRUN#†
I/O
20k(H)
VLPC
Off
Off
Pull-up
Running
ILB_LPC_CLK[1:0]†
I/O
20k(L)
VLPC
Off
Off
V
OL
Running
LPC_RCOMP
-
VLPC
NOTE: All signals with the “†” symbol are multiplexed and may not be available without configuration.