Intel J1850 FH8065301455200 User Manual
Product codes
FH8065301455200
Datasheet
33
Physical Interfaces
2.16
PCU – Power Management Controller (PMC)
Interface Signals
See
for more details.
2.17
JTAG and Debug Interface Signals
Default Buffer State
Signal Name
Dir
Term
()
Plat.
Power
S4/S5
S3
Reset
Enter S0
PMC_PLTRST#
O
-
V1P8A
Off/V
OL
V
OL
V
OL
->V
OH
V
OH
PMC_PWRBTN#†
I
20k(H)
V1P8A
Off/Pull-up
Pull-up
Pull-up
Pull-up
PMC_RSTBTN#
I
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
PMC_SUSPWRDNACK†
O
-
V1P8A
V
OH
/V
OL
V
OH
/V
OL
V
OH
V
OH
/V
OL
PMC_SUS_STAT#†
O
-
V1P8A
V
OL
V
OL
V
OL
V
OH
PMC_SUSCLK[0]†
O
-
V1P8A
Off/Running
Running
Running
Running
PMC_SUSCLK[3:1]†
O
-
PMC_SLP_S3#
O
-
V1P8A
Off/V
OL
V
OL
V
OH
V
OH
PMC_SLP_S4#
O
-
V1P8A
Off/V
OL
V
OH
V
OH
V
OH
PMC_WAKE_PCIE[0]#
I
20k(H)
V1P8A
Off/Pull-up
Pull-up
Pull-up
Pull-up
PMC_WAKE_PCIE[3:1]#†
I
20k(H)
V1P8A
Off/Pull-up
Pull-up
Pull-up
Pull-up
PMC_ACPRESENT
I
20k(L)
V1P8A
Off/High-Z
Pull-down
Pull-down
Pull-down
PMC_BATLOW#
I
20k(H)
V1P8A
Off/Pull-up
Pull-up
Pull-up
Pull-up
PMC_CORE_PWROK
I
VRTC
V
IL
V
IL
V
IL
V
IH
PMC_RSMRST#
I
VRTC
V
IH
V
IH
V
IH
V
IH
NOTE: All signals with the “†” symbol are multiplexed and may not be available without configuration.
Table 17. JTAG and Debug Interface Signals
Default Buffer State
Signal Name
Dir
Term
()
Plat.
Power
S4/S5
S3
Reset
Enter S0
TAP_TCK
I
2k(L)
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
TAP_TDI
I
2k(H)
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
TAP_TDO
O
-
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
TAP_TMS
I
2k(H)
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
TAP_TRST#
I
2k(H)
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
TAP_PRDY#
O
2k(H)
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
TAP_PREQ#
I
2k(H)
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up