Intel J1850 FH8065301455200 User Manual
Product codes
FH8065301455200
Datasheet
41
Physical Interfaces
2.21
Hardware Straps
All straps are sampled on the rising edge of PMC_CORE_PWROK. Defaults are based on
internal termination.
internal termination.
2.22
Configurable IO – GPIO Multiplexing
Not all interfaces may be active at the same time. To provide flexibility, some interfaces
are multiplexed with configurable IO balls. An interface’s signal is selected by a function
number..
are multiplexed with configurable IO balls. An interface’s signal is selected by a function
number..
Note:
Configurable IO defaults to function 0 at boot. All configurable IO with GPIOs for
function 0 default to input at boot.
function 0 default to input at boot.
§
Table 23. Straps
Signal Name
Function
Default
Strap Exit
Strap Description
GPIO_S0_SC[056]
Legacy
1b
PMC_CORE_PWROK de-
asserted
Top Swap (A16 Override)
0 = Top address bit is unchanged
1 = Top address bit is inverted
0 = Top address bit is unchanged
1 = Top address bit is inverted
GPIO_S0_SC[063]
Legacy
1b
PMC_CORE_PWROK de-
asserted
BIOS Boot Selection
0 = LPC
1 = SPI
0 = LPC
1 = SPI
GPIO_S0_SC[065]
Legacy
1b
PMC_CORE_PWROK de-
asserted
Security Flash Descriptors
0 = Override
1 = Normal Operation
0 = Override
1 = Normal Operation
DDI0_DDCDATA
Display
0b
PMC_CORE_PWROK de-
asserted
DDI0 Detect
0 = DDI0 not detected
1 = DDI0 detected
0 = DDI0 not detected
1 = DDI0 detected
DDI1_DDCDATA
Display
0b
PMC_CORE_PWROK de-
asserted
DDI1 Detect
0 = DDI1 not detected
1 = DDI1 detected
0 = DDI1 not detected
1 = DDI1 detected