Intel J1850 FH8065301455200 User Manual

48

Datasheet

The processor supports four different address spaces:

•

•

•

•

Message Bus Space

The CPU core can only directly access memory space through memory reads and writes 
and IO space through the 

IN

 and 

OUT

 IO port instructions. PCI configuration space is 

indirectly accessed through IO or memory space, and the Message Bus space is 
accessed through PCI configuration space. See 

 

for details.

This chapter describes how the memory, IO, PCI, and Message Bus spaces are mapped 
to interfaces in the processor.

See 

 for registers specified in the chapter.

There are 64 GB (36-bits) of physical address space that can be used as:

•

Memory Mapped IO (MMIO – IO fabric)

•

Physical Memory (DRAM)

The CPU core can access the full physical address space, while downstream devices can 
only access processor DRAM, and each CPU core’s local APIC. Peer-to-peer transactions 
are not supported.

Most devices map their registers and memory to the physical address space. This 
section summarizes the possible mappings.

The Processor Transaction Router maps the physical address space as follows:

•

CPU core to DRAM

•

CPU core to IO fabric (MMIO)

•

CPU core to extended PCI registers (ECAM accesses)

•

IO fabric to CPU cores (local APIC interrupts)

Although 64 GB (36-bits) of physical address space is accessible, some MMIO must 
exist for devices and software with 32-bit limits. Further, all DRAM should remain 
accessible for devices and software with access to memory above 4 GB. These goals