Intel J1850 FH8065301455200 User Manual
Product codes
FH8065301455200
Mapping Address Spaces
50
Datasheet
4.1.1.1
Low MMIO
The low MMIO mappings are shown in
.
By default, CPU core reads targeting the Boot Vector range (FFFFFFFFh–FFFF0000h)
are sent to the boot Flash connected to the Platform Controller Unit, and write accesses
target DRAM. This allows the boot strap CPU core to fetch boot code from the boot
Flash, and then shadow that code to DRAM.
are sent to the boot Flash connected to the Platform Controller Unit, and write accesses
target DRAM. This allows the boot strap CPU core to fetch boot code from the boot
Flash, and then shadow that code to DRAM.
Upstream writes from the IO fabric to the Local APIC range (FEE00000h–FEF00000h)
are sent to the appropriate CPU core’s APIC.
are sent to the appropriate CPU core’s APIC.
Write accesses from a CPU core to the Abort Page range (FEB00000h–FEBFFFFFh) will
be dropped, and reads will always return all 1s in binary.
be dropped, and reads will always return all 1s in binary.
Figure 3.
Physical Address Space – Low MMIO
Low DRAM
DOS DRAM
High MMIO
Low MMIO
4 GB
64 GB
1 MB
Physical Address
Space
High DRAM
BMBOUND
- 1
(FFFFFFFFh)
- 20 MB
(FEBFFFFFh)
- 21 MB
(FEB00000h)
Abort Page
- 64 KB
(FFFF0000h)
Boot Vector
- 17 MB
(FEF00000h)
- 18 MB
(FEE00000h)
Local APIC
BEGREG + 256 MB
BECREG
PCI ECAM