Intel J1850 FH8065301455200 User Manual

Datasheet

971

This register contains misc. fields used to configure the processor's power management 

behavior.

Default: 00000000h

Type: Memory Mapped I/O Register

(Size: 32 bits)

PMC_BASE_ADDRESS Type: PCI Configuration Register (Size: 

32 bits)
PMC_BASE_ADDRESS Reference: [B:0, D:31, F:0] + 44h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

re

se

rv

ed

sps

no

_reb

oot

sx

_ent

_

to_en

res

er

ved

2

timing_t581

31:6

0b

RO

reserved: Reserved.

5

0b

RW

Shutdown Policy Select (SPS) (sps): When cleared (default) the processor will drive 

INIT# in response to the shutdown Message. When set to 1, processor will treat the 

shutdown message similar to receiving a CF9h I/O write, and will drive PMU_PLTRST 

active. . BIOS guide note: This register is reset any time PMU_PLTRST asserts.

4

0b

RW

No Reboot (NO_REBOOT) (no_reboot): This bit is set when the No Reboot strap is 

sampled high on COREPWROK. This bit may be set or cleared by software if the strap is 

sampled low but may not override the strap when it indicates No Reboot. When set, the 

TCO timer will count down and generate the SMI# on the first timeout, but will not 

reboot on the second timeout.

3

0b

RW

S1/3/4/5 Entry Timeout Enable (SX_ENT_TO_EN) (sx_ent_to_en): This policy 

bit determines whether the processor will apply a timeout to the S1/S3/S4/S5 entry 

flow. If this timeout is enabled and the entry flow appears to be hung, the processor will 

trigger a straight-to-S5 global reset. Encodings: 0: Timeout disabled (default) 1: 

Timeout enabled reset_type=RSMRST_B

2

0b

RO

reserved (reserved2): Reserved.

1:0

0b

RW

Timing t581 (TIMING_T581) (timing_t581): This field configures the t581 timing 

involved in the power down flow (CPU Power Good indication inactive to PLL Enable 

inactive). Encodings (all min timings): 00: 10 us (default) 01: 100 us 10: 1 ms 11: 10 

ms reset_type=Resume Well Reset#