Intel J1850 FH8065301455200 User Manual

Datasheet

969

Bits in this register only need to be valid for reading when the Main power well is up. 

However, since some of the events may initially be detected while the Main power well 

is down, they are marked as suspend well bits. All suspend well bits in this register are 

reset by global reset#.

Default: 00000000h

ACh

4

00000000h

B0h

4

00000000h

B4h

4

00000000h

B8h

4

00000000h

BCh

4

00000000h

C0h

4

00000000h

C4h

4

00000000h

C8h

4

00000000h

CCh

4

00000000h

D0h

4

00000000h

D4h

4

00000000h

D8h

4

00000000h

DCh

4

00000000h

Type: Memory Mapped I/O Register

(Size: 32 bits)

PMC_BASE_ADDRESS Type: PCI Configuration Register (Size: 

32 bits)
PMC_BASE_ADDRESS Reference: [B:0, D:31, F:0] + 44h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

pmc_p

rod

id

pm

c_r

ev

id

pmc_w

d

t_s

ts

re

se

rv

ed

cod

e_c

opie

d_s

ts

re

se

rv

ed

1

co

d

e_

lo

ad_

to

pm

c_o

p

_sts

se

c_gb

lrst_s

ts

se

c_wdt_s

ts

wol_ovr_w

k_sts

pmc_hos

t_w

ak

e_s

ts

re

se

rv

ed

2

31:24

0b

RO

Power Management Controller Product ID (PMC_PRODID) (pmc_prodid): This 

field communicates the Product Family of the power management functionality