Intel Phi 7120A SC7120A Data Sheet
Product codes
SC7120A
Document ID Number: 328209 003EN
Intel
®
Xeon Phi™ Coprocessor Datasheet
19
Within 50ns of detecting T
throttle
, the DTS circuit begins stepping down the P-states
until Pn is reached. Each frequency step is approximately 100MHz; the exact value will
depend on the starting frequency. After each step, the DTS will wait 10uS before taking
the next step. The number of steps, or P-states, depends on the starting frequency and
the minimum frequency supported by the processor. Once Pn is reached, the frequency
will be held at that level for approximately 1ms, or until the temperature has dropped
below Tprochot, whichever is longer.
depend on the starting frequency. After each step, the DTS will wait 10uS before taking
the next step. The number of steps, or P-states, depends on the starting frequency and
the minimum frequency supported by the processor. Once Pn is reached, the frequency
will be held at that level for approximately 1ms, or until the temperature has dropped
below Tprochot, whichever is longer.
If throttling continues for more than 100ms, the coprocessor OS will reduce the voltage
setting in order to further decrease the power dissipation. The voltage settings are pre-
programmed at the factory and cannot be reconfigured.
setting in order to further decrease the power dissipation. The voltage settings are pre-
programmed at the factory and cannot be reconfigured.
Upon removal of the thermal event, the process reverses and the voltage and
frequency are stepped back up to the P1 state. Although the process to reduce
frequency is managed by the coprocessor circuits, the sequence to bring the
coprocessor back to P1 is controlled by the coprocessor OS. As a result, the precise
timings of the step changes may be slightly longer than 10uS.
frequency are stepped back up to the P1 state. Although the process to reduce
frequency is managed by the coprocessor circuits, the sequence to bring the
coprocessor back to P1 is controlled by the coprocessor OS. As a result, the precise
timings of the step changes may be slightly longer than 10uS.
3.3
Intel
®
Xeon Phi™ Coprocessor Thermal Solutions
There are two types of thermal solutions to address the Intel
®
Xeon Phi™ coprocessor
power limits: a passive solution for most SKUs as indicated in
(which relies on
forced convection airflow provided by the system) and an active solution on the 3120A
and 7120A SKUs (which uses a high performance blower.) The active solution is
designed to operate in an 'adjacent card configuration' such that the impedance from a
nearby flow blockage is accounted for within the design. Both passive and active
solutions come with cooling backplates that augment the stiffness of the Intel
and 7120A SKUs (which uses a high performance blower.) The active solution is
designed to operate in an 'adjacent card configuration' such that the impedance from a
nearby flow blockage is accounted for within the design. Both passive and active
solutions come with cooling backplates that augment the stiffness of the Intel
®
Xeon
Phi™ coprocessor card by counteracting the preload applied by the primary side
(housing the coprocessor). This also protects the structural integrity of the coprocessor
and GDDR packages during a shock event, and to provide a protective cover.
(housing the coprocessor). This also protects the structural integrity of the coprocessor
and GDDR packages during a shock event, and to provide a protective cover.
Given the requirement to dissipate backside GDDR heat within the 2.67 mm keep-in
height prescribed by the PCI Express* specification, the backplate is designed to
transfer the GDDR heat from the secondary side via heat pipes to the primary side
thermal solution.
height prescribed by the PCI Express* specification, the backplate is designed to
transfer the GDDR heat from the secondary side via heat pipes to the primary side
thermal solution.
Figure 3-3
Entering and Exiting Thermal Throttling (PROCHOT)