Intel i3-4360T CM8064601481958 User Manual

be on opposite channels. Use Dual-Channel Symmetric mode when both Channel A

and Channel B DIMM connectors are populated in any order, with the total amount of

memory in each channel being the same.

When both channels are populated with the same memory capacity and the boundary

between the dual channel zone and the single channel zone is the top of memory, the

IMC operates completely in Dual-Channel Symmetric mode.

The DRAM device technology and width may vary from one channel to the other.

In all modes, the frequency of system memory is the lowest frequency of all memory

modules placed in the system, as determined through the SPD registers on the

memory modules. The system memory controller supports one or two DIMM

connectors per channel. The usage of DIMM modules with different latencies is

allowed, but in that case, the worst latency (among two channels) will be used. For

dual-channel modes, both channels must have a DIMM connector populated and for

single-channel mode only a single channel may have one or both DIMM connectors

populated.

In a two-DIMM Per Channel (2DPC) layout memory configuration, the furthest DIMM

from the processor of any given channel must always be populated first.

The following sections describe the Just-in-Time Scheduling, Command Overlap, and

Out-of-Order Scheduling Intel FMA technology enhancements.

The memory controller has an advanced command scheduler where all pending

requests are examined simultaneously to determine the most efficient request to be

issued next. The most efficient request is picked from all pending requests and issued

to system memory Just-in-Time to make optimal use of Command Overlapping. Thus,

instead of having all memory access requests go individually through an arbitration

mechanism forcing requests to be executed one at a time, the requests can be started

without interfering with the current request allowing for concurrent issuing of

requests. This allows for optimized bandwidth and reduced latency while maintaining

appropriate command spacing to meet system memory protocol.

Command Overlap allows the insertion of the DRAM commands between the Activate,

Pre-charge, and Read/Write commands normally used, as long as the inserted

commands do not affect the currently executing command. Multiple commands can be

issued in an overlapping manner, increasing the efficiency of system memory protocol.

While leveraging the Just-in-Time Scheduling and Command Overlap enhancements,

the IMC continuously monitors pending requests to system memory for the best use of

bandwidth and reduction of latency. If there are multiple requests to the same open

page, these requests would be launched in a back-to-back manner to make optimum

use of the open memory page. This ability to reorder requests on the fly allows the

IMC to further reduce latency and increase bandwidth efficiency.

Desktop 4th Generation Intel

®

 Core

™

 Processor Family, Desktop Intel

®

 Pentium

®

 Processor Family, and Desktop Intel

®

 Celeron

®

Processor Family

Datasheet – Volume 1 of 2

July 2014

22

Order No.: 328897-009