Intel i3-4360T CM8064601481958 User Manual

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PCI Express* extended configuration space. The first 256 bytes of configuration

space aliases directly to the PCI Compatibility configuration space. The remaining

portion of the fixed 4-KB block of memory-mapped space above that (starting at

100h) is known as extended configuration space.

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PCI Express* Enhanced Access Mechanism. Accessing the device configuration

space in a flat memory mapped fashion.

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Automatic discovery, negotiation, and training of link out of reset.

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Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering).

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Peer segment destination posted write traffic (no peer-to-peer read traffic) in

Virtual Channel 0: DMI -> PCI Express* Port 0

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64-bit downstream address format, but the processor never generates an address

above 64 GB (Bits 63:36 will always be zeros).

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64-bit upstream address format, but the processor responds to upstream read

transactions to addresses above 64 GB (addresses where any of Bits 63:36 are

nonzero) with an Unsupported Request response. Upstream write transactions to

addresses above 64 GB will be dropped.

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Re-issues Configuration cycles that have been previously completed with the

Configuration Retry status.

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PCI Express* reference clock is 100-MHz differential clock.

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Power Management Event (PME) functions.

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Dynamic width capability.

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Message Signaled Interrupt (MSI and MSI-X) messages.

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Polarity inversion

The processor does not support PCI Express* Hot-Plug.

Compatibility with the PCI addressing model is maintained to ensure that all existing

applications and drivers operate unchanged.

The PCI Express* configuration uses standard mechanisms as defined in the PCI Plug-

and-Play specification. The processor PCI Express* ports support Gen 3. At 8 GT/s,

Gen 3 operation results in twice as much bandwidth per lane as compared to Gen 2

operation. The 16 lanes PEG can operate at 2.5 GT/s, 5 GT/s, or 8 GT/s.

Gen 3 PCI Express* uses a 128b/130b encoding that is about 23% more efficient than

the 8b/10b encoding used in Gen 1 and Gen 2.

The PCI Express* architecture is specified in three layers – Transaction Layer, Data

Link Layer, and Physical Layer. See the PCI Express Base Specification 3.0 for details

of PCI Express* architecture.

The PCI Express* (external graphics) link is mapped through a PCI-to-PCI bridge

structure.

Desktop 4th Generation Intel

®

 Core

™

 Processor Family, Desktop Intel

®

 Pentium

®

 Processor Family, and Desktop Intel

®

 Celeron

®

Processor Family

Datasheet – Volume 1 of 2

July 2014

24

Order No.: 328897-009