Intel i3-4360T CM8064601481958 User Manual

The system memory controller incorporates a Data Scrambling feature to minimize the

impact of excessive di/dt on the platform system memory VRs due to successive 1s

and 0s on the data bus. Past experience has demonstrated that traffic on the data bus

is not random and can have energy concentrated at specific spectral harmonics

creating high di/dt, which is generally limited by data patterns that excite resonance

between the package inductance and on die capacitances. As a result, the system

memory controller uses a data scrambling feature to create pseudo-random patterns

on the system memory data bus to reduce the impact of any excessive di/dt.

This section describes the PCI Express* interface capabilities of the processor. See the

PCI Express Base* Specification 3.0 for details on PCI Express*.

The PCI Express* lanes (PEG[15:0] TX and RX) are fully-compliant to the PCI Express

Base Specification, Revision 3.0.

The 4th Generation Intel

®

 Core

™

 processor Desktop with Desktop PCH supports the

configurations shown in the following table (may vary depending on PCH SKUs).

1x8, 2x4

GFX, I/O

2x8

GFX, I/O

1x16

GFX, I/O

•

The port may negotiate down to narrower widths.
— Support for x16/x8/x4/x2/x1 widths for a single PCI Express* mode.

•

2.5 GT/s, 5.0 GT/s and 8 GT/s PCI Express* bit rates are supported.

•

Gen1 Raw bit-rate on the data pins of 2.5 GT/s, resulting in a real bandwidth per

pair of 250 MB/s given the 8b/10b encoding used to transmit data across this

interface. This also does not account for packet overhead and link maintenance.

Maximum theoretical bandwidth on the interface of 4 GB/s in each direction

simultaneously, for an aggregate of 8 GB/s when x16 Gen 1.

•

Gen 2 Raw bit-rate on the data pins of 5.0 GT/s, resulting in a real bandwidth per

pair of 500 MB/s given the 8b/10b encoding used to transmit data across this

interface. This also does not account for packet overhead and link maintenance.

Maximum theoretical bandwidth on the interface of 8 GB/s in each direction

simultaneously, for an aggregate of 16 GB/s when x16 Gen 2.

•

Gen 3 raw bit-rate on the data pins of 8.0 GT/s, resulting in a real bandwidth per

pair of 984 MB/s using 128b/130b encoding to transmit data across this interface.

This also does not account for packet overhead and link maintenance. Maximum

theoretical bandwidth on the interface of 16 GB/s in each direction simultaneously,

for an aggregate of 32 GB/s when x16 Gen 3.

•

Hierarchical PCI-compliant configuration mechanism for downstream devices.

•

Traditional PCI style traffic (asynchronous snooped, PCI ordering).

Desktop 4th Generation Intel

®

 Core

™

 Processor Family, Desktop Intel

®

 Pentium

®

 Processor Family, and Desktop Intel

®

 Celeron

®

Processor Family

July 2014

Datasheet – Volume 1 of 2

Order No.: 328897-009

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