Microchip Technology MCU PIC PIC18F87K22-I/PTRSL TQFP-80 MCP PIC18F87K22-I/PTRSL Data Sheet
Product codes
PIC18F87K22-I/PTRSL
PIC18F87K22 FAMILY
DS39960D-page 170
2009-2011 Microchip Technology Inc.
12.2
PORTA, TRISA and
LATA Registers
LATA Registers
PORTA is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction and Output Latch registers are
TRISA and LATA.
RA4/T0CKI is a Schmitt Trigger input. All other PORTA
pins have TTL input levels and full CMOS output
drivers.
RA5 and RA<3:0> are multiplexed with analog inputs
for the A/D Converter.
The operation of the analog inputs as A/D Converter
inputs is selected by clearing or setting the ANSEL
control bits in the ANCON1 register. The corresponding
TRISA bits control the direction of these pins, even
when they are being used as analog inputs. The user
must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
sponding Data Direction and Output Latch registers are
TRISA and LATA.
RA4/T0CKI is a Schmitt Trigger input. All other PORTA
pins have TTL input levels and full CMOS output
drivers.
RA5 and RA<3:0> are multiplexed with analog inputs
for the A/D Converter.
The operation of the analog inputs as A/D Converter
inputs is selected by clearing or setting the ANSEL
control bits in the ANCON1 register. The corresponding
TRISA bits control the direction of these pins, even
when they are being used as analog inputs. The user
must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
OSC2/CLKO/RA6 and OSC1/CLKI/RA7 normally
serve as the external circuit connections for the exter-
nal (primary) oscillator circuit (HS Oscillator modes), or
the external clock input and output (EC Oscillator
modes). In these cases, RA6 and RA7 are not available
as digital I/O and their corresponding TRIS and LAT
bits are read as ‘0’. When the device is configured to
use HF-INTOSC, MF-INTOSC or LF-INTOSC as the
default oscillator mode, RA6 and RA7 are automatically
configured as digital I/O; the oscillator and clock
in/clock out functions are disabled.
RA5 has additional functionality for Timer1 and Timer3.
It can be configured as the Timer1 clock input or the
Timer3 external clock gate input.
serve as the external circuit connections for the exter-
nal (primary) oscillator circuit (HS Oscillator modes), or
the external clock input and output (EC Oscillator
modes). In these cases, RA6 and RA7 are not available
as digital I/O and their corresponding TRIS and LAT
bits are read as ‘0’. When the device is configured to
use HF-INTOSC, MF-INTOSC or LF-INTOSC as the
default oscillator mode, RA6 and RA7 are automatically
configured as digital I/O; the oscillator and clock
in/clock out functions are disabled.
RA5 has additional functionality for Timer1 and Timer3.
It can be configured as the Timer1 clock input or the
Timer3 external clock gate input.
EXAMPLE 12-1:
INITIALIZING PORTA
Note:
RA5 and RA<3:0> are configured as
analog inputs on any Reset and are read
as ‘0’. RA4 is configured as a digital input.
analog inputs on any Reset and are read
as ‘0’. RA4 is configured as a digital input.
CLRF
PORTA
; Initialize PORTA by
; clearing output latches
CLRF
LATA
; Alternate method to
; clear output data latches
BANKSEL
ANCON1
; Select bank with ANCON1 register
MOVLW
00h
; Configure A/D
MOVWF
ANCON1
; for digital inputs
BANKSEL
TRISA
; Select bank with TRISA register
MOVLW
0BFh
; Value used to initialize
; data direction
MOVWF
TRISA
; Set RA<7, 5:0> as inputs,
; RA<6> as output