Microchip Technology MCU PIC PIC18F87K22-I/PTRSL TQFP-80 MCP PIC18F87K22-I/PTRSL Data Sheet
Product codes
PIC18F87K22-I/PTRSL
PIC18F87K22 FAMILY
DS39960D-page 218
2009-2011 Microchip Technology Inc.
16.5.2
TIMER3/5/7 GATE SOURCE
SELECTION
SELECTION
The Timer3/5/7 gate source can be selected from one
of four different sources. Source selection is controlled
by the TxGSS<1:0> bits (TxGCON<1:0>). The polarity
for each available source is also selectable and is
controlled by the TxGPOL bit (TxGCON <6>).
of four different sources. Source selection is controlled
by the TxGSS<1:0> bits (TxGCON<1:0>). The polarity
for each available source is also selectable and is
controlled by the TxGPOL bit (TxGCON <6>).
TABLE 16-2:
TIMER3/5/7 GATE SOURCES
16.5.2.1
TxG Pin Gate Operation
The TxG pin is one source for Timer3/5/7 gate control. It
can be used to supply an external source to the Timerx
gate circuitry.
can be used to supply an external source to the Timerx
gate circuitry.
16.5.2.2
Timer4/6/8 Match Gate Operation
The TMR(x+1) register will increment until it matches the
value in the PR(x+1) register. On the very next increment
cycle, TMR2 will be reset to 00h. When this Reset
occurs, a low-to-high pulse will automatically be gener-
ated and internally supplied to the Timerx gate circuitry.
The pulse will remain high for one instruction cycle and
will return back to a low state until the next match.
Depending on TxGPOL, Timerx increments differently
when TMR(x+1) matches PR(x+1). When
TxGPOL = 1, Timerx increments for a single instruction
value in the PR(x+1) register. On the very next increment
cycle, TMR2 will be reset to 00h. When this Reset
occurs, a low-to-high pulse will automatically be gener-
ated and internally supplied to the Timerx gate circuitry.
The pulse will remain high for one instruction cycle and
will return back to a low state until the next match.
Depending on TxGPOL, Timerx increments differently
when TMR(x+1) matches PR(x+1). When
TxGPOL = 1, Timerx increments for a single instruction
cycle following a TMR(x+1) match with PR(x+1). When
TxGPOL = 0, Timerx increments continuously, except
for the cycle following the match, when the gate signal
goes from low-to-high.
TxGPOL = 0, Timerx increments continuously, except
for the cycle following the match, when the gate signal
goes from low-to-high.
16.5.2.3
Comparator 1 Output Gate
Operation
Operation
The output of Comparator 1 can be internally supplied
to the Timerx gate circuitry. After setting up
Comparator 1 with the CM1CON register, Timerx will
increment depending on the transitions of the
CMP1OUT (CMSTAT<5>) bit.
to the Timerx gate circuitry. After setting up
Comparator 1 with the CM1CON register, Timerx will
increment depending on the transitions of the
CMP1OUT (CMSTAT<5>) bit.
16.5.2.4
Comparator 2 Output Gate
Operation
Operation
The output of Comparator 2 can be internally supplied
to the Timerx gate circuitry. After setting up
Comparator 2 with the CM2CON register, Timerx will
increment depending on the transitions of the
CMP2OUT (CMSTAT<6>) bit.
to the Timerx gate circuitry. After setting up
Comparator 2 with the CM2CON register, Timerx will
increment depending on the transitions of the
CMP2OUT (CMSTAT<6>) bit.
16.5.3
TIMER3/5/7 GATE TOGGLE MODE
When Timer3/5/7 Gate Toggle mode is enabled, it is
possible to measure the full cycle length of a Timer3/5/7
gate signal, as opposed to the duration of a single level
pulse.
The Timerx gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. (For timing details, see
possible to measure the full cycle length of a Timer3/5/7
gate signal, as opposed to the duration of a single level
pulse.
The Timerx gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. (For timing details, see
The TxGVAL bit will indicate when the Toggled mode is
active and the timer is counting.
Timer3/5/7 Gate Toggle mode is enabled by setting the
TxGTM bit (TxGCON<5>). When the TxGTM bit is
cleared, the flip-flop is cleared and held clear. This is
necessary in order to control which edge is measured.
active and the timer is counting.
Timer3/5/7 Gate Toggle mode is enabled by setting the
TxGTM bit (TxGCON<5>). When the TxGTM bit is
cleared, the flip-flop is cleared and held clear. This is
necessary in order to control which edge is measured.
FIGURE 16-3:
TIMER3/5/7 GATE TOGGLE MODE
TxGSS<1:0>
Timerx Gate Source
00
Timerx Gate Pin
01
TMR(x+1) to Match PR(x+1)
(TMR(x+1) increments to match
PR(x+1))
(TMR(x+1) increments to match
PR(x+1))
10
Comparator 1 Output
(comparator logic high output)
(comparator logic high output)
11
Comparator 2 Output
(comparator logic high output)
(comparator logic high output)
TMRxGE
TxGPOL
TxGTM
TxG_IN
TxCKI
TxGVAL
Timer3/5/7
N
N + 1 N + 2 N + 3
N + 4
N + 5 N + 6 N + 7
N + 8