Microchip Technology MCU PIC PIC18F87K22-I/PTRSL TQFP-80 MCP PIC18F87K22-I/PTRSL Data Sheet
Product codes
PIC18F87K22-I/PTRSL
PIC18F87K22 FAMILY
DS39960D-page 220
2009-2011 Microchip Technology Inc.
FIGURE 16-5:
TIMER3/5/7 GATE SINGLE PULSE AND TOGGLE COMBINED MODE
16.5.5
TIMER3/5/7 GATE VALUE STATUS
When Timer3/5/7 gate value status is utilized, it is
possible to read the most current level of the gate con-
trol value. The value is stored in the TxGVAL bit
(TxGCON<2>). The TxGVAL bit is valid even when the
Timer3/5/7 gate is not enabled (TMRxGE bit is
cleared).
possible to read the most current level of the gate con-
trol value. The value is stored in the TxGVAL bit
(TxGCON<2>). The TxGVAL bit is valid even when the
Timer3/5/7 gate is not enabled (TMRxGE bit is
cleared).
16.5.6
TIMER3/5/7 GATE EVENT
INTERRUPT
INTERRUPT
When the Timer3/5/7 gate event interrupt is enabled, it
is possible to generate an interrupt upon the comple-
tion of a gate event. When the falling edge of TxGVAL
occurs, the TMRxGIF flag bit in the PIRx register will be
set. If the TMRxGIE bit in the PIEx register is set, then
an interrupt will be recognized.
The TMRxGIF flag bit operates even when the
Timer3/5/7 gate is not enabled (TMRxGE bit is
cleared).
is possible to generate an interrupt upon the comple-
tion of a gate event. When the falling edge of TxGVAL
occurs, the TMRxGIF flag bit in the PIRx register will be
set. If the TMRxGIE bit in the PIEx register is set, then
an interrupt will be recognized.
The TMRxGIF flag bit operates even when the
Timer3/5/7 gate is not enabled (TMRxGE bit is
cleared).
TMRxGE
TxGPOL
TxG_IN
TxCKI
TxGVAL
Timer3/5/7
N
N + 1
N + 2
TxGSPM
TxGGO/
TxDONE
Set by Software
Cleared by Hardware on
Falling Edge of TxGVAL
Falling Edge of TxGVAL
Set by Hardware on
Falling Edge of TxGVAL
Cleared by Software
Cleared by
Software
Software
TMRxGIF
TxGTM
Counting Enabled on
Rising Edge of TxG
N + 4
N + 3