Microchip Technology MCU PIC PIC18F87K22-I/PTRSL TQFP-80 MCP PIC18F87K22-I/PTRSL Data Sheet
Product codes
PIC18F87K22-I/PTRSL
PIC18F87K22 FAMILY
DS39960D-page 320
2009-2011 Microchip Technology Inc.
21.4.12
ACKNOWLEDGE SEQUENCE
TIMING
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPxCON2<4>). When this bit is set, the SCLx pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDAx pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate Gen-
erator then counts for one rollover period (T
Acknowledge Sequence Enable bit, ACKEN
(SSPxCON2<4>). When this bit is set, the SCLx pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDAx pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate Gen-
erator then counts for one rollover period (T
BRG
) and the
SCLx pin is deasserted (pulled high). When the SCLx pin
is sampled high (clock arbitration), the Baud Rate Gener-
ator counts for T
is sampled high (clock arbitration), the Baud Rate Gener-
ator counts for T
BRG
; the SCLx pin is then pulled low.
Following this, the ACKEN bit is automatically cleared, the
Baud Rate Generator is turned off and the MSSP module
then goes into an inactive state (
Baud Rate Generator is turned off and the MSSP module
then goes into an inactive state (
).
21.4.12.1
WCOL Status Flag
If the user writes the SSPxBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
21.4.13
STOP CONDITION TIMING
A Stop bit is asserted on the SDAx pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPxCON2<2>). At the end of a
receive/transmit, the SCLx line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDAx line low. When the
SDAx line is sampled low, the Baud Rate Generator is
reloaded and counts down to 0. When the Baud Rate
Generator times out, the SCLx pin will be brought high
and one T
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPxCON2<2>). At the end of a
receive/transmit, the SCLx line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDAx line low. When the
SDAx line is sampled low, the Baud Rate Generator is
reloaded and counts down to 0. When the Baud Rate
Generator times out, the SCLx pin will be brought high
and one T
BRG
(Baud Rate Generator rollover count)
later, the SDAx pin will be deasserted. When the SDAx
pin is sampled high while SCLx is high, the P bit
(SSPxSTAT<4>) is set. A T
pin is sampled high while SCLx is high, the P bit
(SSPxSTAT<4>) is set. A T
BRG
later, the PEN bit is
21.4.13.1
WCOL Status Flag
If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 21-25:
ACKNOWLEDGE SEQUENCE WAVEFORM
FIGURE 21-26:
STOP CONDITION RECEIVE OR TRANSMIT MODE
Note:
T
BRG
= one Baud Rate Generator period.
SDAx
SCLx
SSPxIF Set at
Acknowledge Sequence Starts Here,
Write to SSPxCON2,
ACKEN Automatically Cleared
Cleared in
T
BRG
T
BRG
the End of Receive
8
ACKEN = 1, ACKDT = 0
D0
9
SSPxIF
Software
SSPxIF Set at the End
of Acknowledge Sequence
of Acknowledge Sequence
Cleared in
Software
ACK
SCLx
SDAx
SDAx Asserted Low Before Rising Edge of Clock
Write to SSPxCON2,
Set PEN
Falling Edge of
SCLx = 1 for T
BRG
, Followed by SDAx = 1 for T
BRG
9th Clock
SCLx Brought High After T
BRG
Note:
T
BRG
= one Baud Rate Generator period.
T
BRG
T
BRG
after SDAx Sampled High. P bit (SSPxSTAT<4>) is Set
T
BRG
to Set up Stop Condition
ACK
P
T
BRG
PEN bit (SSPxCON2<2>) is Cleared by
Hardware and the SSPxIF bit is Set
Hardware and the SSPxIF bit is Set