Microchip Technology MCU PIC PIC18F87K22-I/PTRSL TQFP-80 MCP PIC18F87K22-I/PTRSL Data Sheet

Product codes

PIC18F87K22-I/PTRSL

 2009-2011 Microchip Technology Inc.

DS39960D-page 49

PIC18F87K22 FAMILY

The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 4.0
“Power-Managed Modes”

3.3.2.1

System Clock Selection and Device
Resets

Since the SCS bits are cleared on all forms of Reset,
this means the primary oscillator, defined by the
FOSC<3:0> Configuration bits, is used as the primary
clock source on device Resets. This could either be the
internal oscillator block by itself, or one of the other
primary clock source (HS, EC, XT, LP, External RC and
PLL-Enabled modes).
In those cases when the internal oscillator block, with-
out PLL, is the default clock on Reset, the Fast RC
oscillator (INTOSC) will be used as the device clock
source. It will initially start at 8 MHz; the postscaler
selection that corresponds to the Reset value of the
IRCF<2:0> bits (‘110’).
Regardless of which primary oscillator is selected,
INTRC will always be enabled on device power-up. It
serves as the clock source until the device has loaded
its configuration values from memory. It is at this point
that the FOSC Configuration bits are read and the
oscillator selection of the operational mode is made.
Note that either the primary clock source or the internal
oscillator will have two bit setting options for the possible
values of the SCS<1:0> bits, at any given time.

3.3.3

OSCILLATOR TRANSITIONS

PIC18F87K22 family devices contain circuitry to
prevent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs
during the clock switch. The length of this pause is the
sum of two cycles of the old clock source and three to
four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Clock transitions are discussed in greater detail in
Section 4.1.2 “Entering Power-Managed Modes”

3.4

RC Oscillator

For timing-insensitive applications, the RC and RCIO
Oscillator modes offer additional cost savings. The
actual oscillator frequency is a function of several
factors:
• Supply Voltage
• Values of the External Resistor (R

EXT

) and

Capacitor (C

EXT

)

• Operating Temperature
Given the same device, operating voltage and temper-
ature, and component values, there will also be unit to
unit frequency variations. These are due to factors,
such as:
• Normal manufacturing variation
• Difference in lead frame capacitance between

package types (especially for low C

EXT

values)

• Variations within the tolerance of limits of R

EXT

and C

EXT

In the RC Oscillator mode, the oscillator frequency,
divided by 4, is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic.

Figure 3-2

shows how the R/C combination is

connected.

FIGURE 3-2:

RC OSCILLATOR MODE

The RCIO Oscillator mode (

Figure 3-3

) functions like

the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).

FIGURE 3-3:

RCIO OSCILLATOR MODE

Note 1:

The Timer1/3/5/7 oscillator must be
enabled to select the secondary clock
source. The Timerx oscillator is enabled by
setting the SOSCEN bit in the Timerx Con-
trol register (TxCON<3>). If the Timerx
oscillator is not enabled, then any attempt
to select a secondary clock source when
executing a SLEEP instruction will be
ignored.

It is recommended that the Timerx
oscillator be operating and stable before
executing the SLEEP instruction or a very
long delay may occur while the Timerx
oscillator starts.

OSC2/CLKO

EXT

PIC18F87K22

OSC1

OSC

Internal

Clock

Recommended values: 3 k

  R

EXT

 100 k

20 pF

C

EXT

 300 pF

EXT