Microchip Technology MCU PIC PIC18F87K22-I/PTRSL TQFP-80 MCP PIC18F87K22-I/PTRSL Data Sheet
Product codes
PIC18F87K22-I/PTRSL
2009-2011 Microchip Technology Inc.
DS39960D-page 51
PIC18F87K22 FAMILY
3.5.2
EXTERNAL CLOCK INPUT
(EC MODES)
(EC MODES)
The EC and ECPLL Oscillator modes require an
external clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency,
divided by 4, is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic.
external clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency,
divided by 4, is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic.
shows the pin connections for the EC
Oscillator mode.
FIGURE 3-5:
EXTERNAL CLOCK
INPUT OPERATION
(EC CONFIGURATION)
INPUT OPERATION
(EC CONFIGURATION)
An external clock source may also be connected to the
OSC1 pin in HS mode, as shown in
OSC1 pin in HS mode, as shown in
. In this
configuration, the divide-by-4 output on OSC2 is not
available. Current consumption in this configuration will
be somewhat higher than EC mode, as the internal
oscillator’s feedback circuitry will be enabled (in EC
mode, the feedback circuit is disabled).
available. Current consumption in this configuration will
be somewhat higher than EC mode, as the internal
oscillator’s feedback circuitry will be enabled (in EC
mode, the feedback circuit is disabled).
FIGURE 3-6:
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
OPERATION (HS OSC
CONFIGURATION)
3.5.3
PLL FREQUENCY MULTIPLIER
A Phase Locked Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit, or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals, or users who require higher
clock speeds from an internal oscillator.
option for users who want to use a lower frequency
oscillator circuit, or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals, or users who require higher
clock speeds from an internal oscillator.
3.5.3.1
HSPLL and ECPLL Modes
The HSPLL and ECPLL modes provide the ability to
selectively run the device at four times the external
oscillating source to produce frequencies up to
64 MHz.
The PLL is enabled by setting the PLLEN bit
(OSCTUNE<6>) or the PLLCFG bit (CONFIG1H<4>).
The PLLEN bit provides a software control for the PLL,
even if PLLCFG is set to ‘0’. The PLL is enabled only
when the HS or EC oscillator frequency is within the
4 MHz to16 MHz input range.
This enables additional flexibility for controlling the
application’s clock speed in software. The PLLEN
should be enabled in HS or EC Oscillator mode only if
the input frequency is in the range of 4 MHz-16 MHz.
selectively run the device at four times the external
oscillating source to produce frequencies up to
64 MHz.
The PLL is enabled by setting the PLLEN bit
(OSCTUNE<6>) or the PLLCFG bit (CONFIG1H<4>).
The PLLEN bit provides a software control for the PLL,
even if PLLCFG is set to ‘0’. The PLL is enabled only
when the HS or EC oscillator frequency is within the
4 MHz to16 MHz input range.
This enables additional flexibility for controlling the
application’s clock speed in software. The PLLEN
should be enabled in HS or EC Oscillator mode only if
the input frequency is in the range of 4 MHz-16 MHz.
FIGURE 3-7:
PLL BLOCK DIAGRAM
3.5.3.2
PLL and HF-INTOSC
The PLL is available to the internal oscillator block
when the internal oscillator block is configured as the
primary clock source. In this configuration, the PLL is
enabled in software and generates a clock output of up
to 64 MHz.
The operation of INTOSC with the PLL is described in
when the internal oscillator block is configured as the
primary clock source. In this configuration, the PLL is
enabled in software and generates a clock output of up
to 64 MHz.
The operation of INTOSC with the PLL is described in
. Care should be taken
that the PLL is enabled only if the HF-INTOSC
postscaler is configured for 8 MHz or 16 MHz
postscaler is configured for 8 MHz or 16 MHz
.
OSC1/CLKI
OSC2/CLKO
F
OSC
/4
Clock from
Ext. System
Ext. System
PIC18F87K22
OSC1
OSC2
Open
Clock from
Ext. System
Ext. System
(HS Mode)
PIC18F87K22
MU
X
VCO
Loop
Filter
Filter
OSC2
OSC1
PLL Enable (OSCTUNE)
F
IN
F
OUT
SYSCLK
Phase
Comparator
PLLCFG (CONFIG1H<4>)
4
HS or EC
Mode