Microchip Technology MCU PIC PIC18F87K22-I/PTRSL TQFP-80 MCP PIC18F87K22-I/PTRSL Data Sheet
Product codes
PIC18F87K22-I/PTRSL
2011 Microchip Technology Inc.
DS39960D-page 515
PIC18F87K22 FAMILY
FIGURE 31-15:
EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
TABLE 31-18: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
73
T
DI
V2
SC
H,
T
DI
V2
SC
L
Setup Time of SDIx Data Input to SCKx Edge
20
—
ns
73A
T
B
2
B
Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
of Byte 2
1.5 T
CY
+ 40
—
ns
74
T
SC
H2
DI
L,
T
SC
L2
DI
L
Hold Time of SDIx Data Input to SCKx Edge
40
—
ns
75
T
DO
R
SDOx Data Output Rise Time
—
25
ns
76
T
DO
F
SDOx Data Output Fall Time
—
25
ns
78
T
SC
R
SCKx Output Rise Time (Master mode)
—
25
ns
79
T
SC
F
SCKx Output Fall Time (Master mode)
—
25
ns
80
T
SC
H2
DO
V,
T
SC
L2
DO
V
SDOx Data Output Valid after SCKx Edge
—
50
ns
81
T
DO
V2
SC
H,
T
DO
V2
SC
L
SDOx Data Output Setup to SCKx Edge
T
CY
—
ns
SCKx
(CKPx = 0)
(CKPx = 0)
SCKx
(CKPx = 1)
(CKPx = 1)
SDOx
SDIx
81
74
75, 76
78
80
MSb
79
73
bit 6 - - - - - - 1
LSb In
bit 6 - - - - 1
LSb
Note:
for load conditions.
MSb In