Microchip Technology MCU PIC PIC18F87K22-I/PTRSL TQFP-80 MCP PIC18F87K22-I/PTRSL Data Sheet
Product codes
PIC18F87K22-I/PTRSL
2011 Microchip Technology Inc.
DS39960D-page 517
PIC18F87K22 FAMILY
FIGURE 31-17:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
TABLE 31-20: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
T
SS
L2
SC
H,
T
SS
L2
SC
L
SSx
to SCKx or SCKx Input
3 T
CY
—
ns
70A
T
SS
L2WB SSx to Write to SSPBUF
3 T
CY
—
ns
71
T
SC
H
SCKx Input High Time
(Slave mode)
(Slave mode)
Continuous
1.25 T
CY
+ 30 —
ns
71A
Single Byte
40
—
ns
)
72
T
SC
L
SCKx Input Low Time
(Slave mode)
(Slave mode)
Continuous
1.25 T
CY
+ 30 —
ns
72A
Single Byte
40
—
ns
)
73A
T
B
2
B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 T
CY
+ 40
—
ns
)
74
T
SC
H2
DI
L,
T
SC
L2
DI
L
Hold Time of SDIx Data Input to SCKx Edge
40
—
ns
75
T
DO
R
SDOx Data Output Rise Time
—
25
ns
76
T
DO
F
SDOx Data Output Fall Time
—
25
ns
77
T
SS
H2
DO
Z SSx
to SDOx Output High-Impedance
10
50
ns
78
T
SC
R
SCKx Output Rise Time (Master mode)
—
25
ns
79
T
SC
F
SCKx Output Fall Time (Master mode)
—
25
ns
80
T
SC
H2
DO
V,
T
SC
L2
DO
V
SDOx Data Output Valid after SCKx Edge
—
50
ns
82
T
SS
L2
DO
V SDOx Data Output Valid after SSx
Edge
—
50
ns
83
T
SC
H2
SS
H,
T
SC
L2
SS
H
SSx
after SCKx Edge
1.5 T
CY
+ 40
—
ns
Note 1:
Requires the use of Parameter #73A.
2:
Only if Parameter #71A and #72A are used.
SSx
SCKx
(CKPx = 0)
(CKPx = 0)
SCKx
(CKPx = 1)
(CKPx = 1)
SDOx
SDIx
70
71
72
82
74
75, 76
MSb
bit 6 - - - - - - 1
LSb
77
bit 6 - - - - 1
LSb In
80
83
Note:
Refer to
for load conditions.
MSb In