Microchip Technology IC PIC MCU PIC18F65J15-I/PT TQFP-64 MCP PIC18F65J15-I/PT Data Sheet

DS39663F-page 120

© 2009 Microchip Technology Inc.

The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Priority registers (IPR1, IPR2, IPR3). Using
the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set. 
             

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

PSPIP

ADIP

RC1IP

TX1IP

SSP1IP

CCP1IP

TMR2IP

TMR1IP

bit 7

bit 0

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

PSPIP: Parallel Port Read/Write Interrupt Priority bit
1 = High priority 
0 = Low priority

bit 6

ADIP: A/D Converter Interrupt Priority bit
1 = High priority 
0 = Low priority 

bit 5

RC1IP: EUSART1 Receive Interrupt Priority bit 
1 = High priority 
0 = Low priority  

bit 4

TX1IP: EUSART1 Transmit Interrupt Priority bit 

1 = High priority 
0 = Low priority

bit 3

SSP1IP: Master Synchronous Serial Port 1 Interrupt Priority bit 
1 = High priority 
0 = Low priority

bit 2

CCP1IP: ECCP1 Interrupt Priority bit 
1 = High priority 
0 = Low priority

bit 1

TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 
1 = High priority 
0 = Low priority

bit 0

TMR1IP: TMR1 Overflow Interrupt Priority bit 
1 = High priority 
0 = Low priority