Microchip Technology IC PIC MCU PIC18F65J15-I/PT TQFP-64 MCP PIC18F65J15-I/PT Data Sheet
Product codes
PIC18F65J15-I/PT
© 2009 Microchip Technology Inc.
DS39663F-page 121
PIC18F87J10 FAMILY
REGISTER 10-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1
R/W-1
U-0
U-0
R/W-1
U-0
R/W-1
R/W-1
OSCFIP
CMIP
—
—
BCL1IP
—
TMR3IP
CCP2IP
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
OSCFIP: Oscillator Fail Interrupt Priority bit
1 = High priority
0 = Low priority
1 = High priority
0 = Low priority
bit 6
CMIP: Comparator Interrupt Priority bit
1 = High priority
0 = Low priority
1 = High priority
0 = Low priority
bit 5-4
Unimplemented: Read as ‘0’
bit 3
BCL1IP: Bus Collision Interrupt Priority bit (MSSP1 module)
1 = High priority
0 = Low priority
1 = High priority
0 = Low priority
bit 2
Unimplemented: Read as ‘0’
bit 1
TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
1 = High priority
0 = Low priority
bit 0
CCP2IP: ECCP2 Interrupt Priority bit
1 = High priority
0 = Low priority
1 = High priority
0 = Low priority