Microchip Technology IC PIC MCU PIC18F65J15-I/PT TQFP-64 MCP PIC18F65J15-I/PT Data Sheet
Product codes
PIC18F65J15-I/PT
© 2009 Microchip Technology Inc.
DS39663F-page 125
PIC18F87J10 FAMILY
11.0 I/O PORTS
Depending on the device selected and features
enabled, there are up to nine ports available. Some
pins of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
enabled, there are up to nine ports available. Some
pins of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (Output Latch register)
The Output Latch (LAT register) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 11-1.
The Output Latch (LAT register) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 11-1.
FIGURE 11-1:
GENERIC I/O PORT
OPERATION
OPERATION
11.1
I/O Port Pin Capabilities
When developing an application, the capabilities of the
port pins must be considered. Outputs on some pins
have higher output drive strength than others. Similarly,
some pins can tolerate higher than V
port pins must be considered. Outputs on some pins
have higher output drive strength than others. Similarly,
some pins can tolerate higher than V
DD
input levels.
11.1.1
PIN OUTPUT DRIVE
The output pin drive strengths vary for groups of pins
intended to meet the needs for a variety of applications.
PORTB and PORTC are designed to drive higher
loads, such as LEDs. The external memory interface
ports (PORTD, PORTE and PORTJ) are designed to
drive medium loads. All other ports are designed for
small loads, typically indication only. Table 11-1 sum-
marizes the output capabilities. Refer to Section 27.0
“Electrical Characteristics” for more details.
intended to meet the needs for a variety of applications.
PORTB and PORTC are designed to drive higher
loads, such as LEDs. The external memory interface
ports (PORTD, PORTE and PORTJ) are designed to
drive medium loads. All other ports are designed for
small loads, typically indication only. Table 11-1 sum-
marizes the output capabilities. Refer to Section 27.0
“Electrical Characteristics” for more details.
TABLE 11-1:
OUTPUT DRIVE LEVELS
Data
Bus
WR LAT
WR TRIS
RD Port
Data Latch
TRIS Latch
RD TRIS
Input
Buffer
I/O pin
(1)
Q
D
CK
Q
D
CK
EN
Q
D
EN
RD LAT
or Port
Port
Drive
Description
PORTA
Minimum Intended for indication.
PORTF
PORTG
PORTH
PORTG
PORTH
(1)
PORTD
Medium Sufficient drive levels for
external memory interfacing
as well as indication.
as well as indication.
PORTE
PORTJ
PORTJ
(1)
PORTB
High
Suitable for direct LED drive
levels.
levels.
PORTC
Note 1: These ports are not available on 64-pin
Note 1: These ports are not available on 64-pin
devices.