Microchip Technology IC PIC MCU PIC18F65J15-I/PT TQFP-64 MCP PIC18F65J15-I/PT Data Sheet
Product codes
PIC18F65J15-I/PT
PIC18F87J10 FAMILY
DS39663F-page 126
© 2009 Microchip Technology Inc.
11.1.2
INPUT PINS AND VOLTAGE
CONSIDERATIONS
CONSIDERATIONS
The voltage tolerance of pins used as device inputs is
dependent on the pin’s input function. Pins that are used
as digital only inputs are able to handle DC voltages up
to 5.5V, a level typical for digital logic circuits. In contrast,
pins that also have analog input functions of any kind
can only tolerate voltages up to V
dependent on the pin’s input function. Pins that are used
as digital only inputs are able to handle DC voltages up
to 5.5V, a level typical for digital logic circuits. In contrast,
pins that also have analog input functions of any kind
can only tolerate voltages up to V
DD
. Voltage excursions
beyond V
DD
on these pins should be avoided.
Table 11-2 summarizes the input capabilities. Refer to
Section 27.0 “Electrical Characteristics” for more
details.
Section 27.0 “Electrical Characteristics” for more
details.
TABLE 11-2:
INPUT VOLTAGE LEVELS
11.2
PORTA, TRISA and
LATA Registers
LATA Registers
PORTA is a 6-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the port latch.
The Output Latch register (LATA) is also memory
mapped. Read-modify-write operations on the LATA
register read and write the latched output value for
PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The other
PORTA pins are multiplexed with the analog V
sponding Data Direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the port latch.
The Output Latch register (LATA) is also memory
mapped. Read-modify-write operations on the LATA
register read and write the latched output value for
PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The other
PORTA pins are multiplexed with the analog V
REF
+ and
V
REF
- inputs. The operation of pins RA<5:0> as A/D
Converter inputs is selected by clearing or setting the
PCFG<3:0> control bits in the ADCON1 register.
PCFG<3:0> control bits in the ADCON1 register.
The RA4/T0CKI pin is a Schmitt Trigger input. All other
PORTA pins have TTL input levels and full CMOS
output drivers.
The TRISA register controls the direction of the PORTA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
PORTA pins have TTL input levels and full CMOS
output drivers.
The TRISA register controls the direction of the PORTA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 11-1:
INITIALIZING PORTA
Port or Pin
Tolerated
Input
Description
PORTA<5:0>
V
DD
Only V
DD
input levels
tolerated.
PORTC<1:0>
PORTF<6:1>
PORTH<7:4>
PORTF<6:1>
PORTH<7:4>
(1)
PORTB<7:0>
5.5V
Tolerates input levels
above V
above V
DD
, useful for
most standard logic.
PORTC<7:2>
PORTD<7:0>
PORTE<7:0>
PORTF<7>
PORTG<4:0>
PORTH<3:0>
PORTD<7:0>
PORTE<7:0>
PORTF<7>
PORTG<4:0>
PORTH<3:0>
(1)
PORTJ<7:0>
(1)
Note 1:
These ports are not available on 64-pin
devices.
devices.
Note:
RA5 and RA<3:0> are configured as
analog inputs on any Reset and are read
as ‘0’. RA4 is configured as a digital input.
analog inputs on any Reset and are read
as ‘0’. RA4 is configured as a digital input.
CLRF
PORTA
; Initialize PORTA by
; clearing output
; data latches
; clearing output
; data latches
CLRF
LATA
; Alternate method
; to clear output
; data latches
; to clear output
; data latches
MOVLW
07h
; Configure A/D
MOVWF
ADCON1 ; for digital inputs
MOVWF
07h
; Configure comparators
MOVWF
CMCON
; for digital input
MOVLW
0CFh
; Value used to
; initialize data
; direction
; initialize data
; direction
MOVWF
TRISA
; Set RA<3:0> as inputs
; RA<5:4> as outputs
; RA<5:4> as outputs