Microchip Technology IC PIC MCU PIC18F65J15-I/PT TQFP-64 MCP PIC18F65J15-I/PT Data Sheet

DS39663F-page 144

© 2009 Microchip Technology Inc.

PORTH is an 8-bit wide, bidirectional I/O port. The cor-
responding Data Direction register is TRISH. Setting a
TRISH bit (= 1) will make the corresponding PORTH
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISH bit (= 0)
will make the corresponding PORTH pin an output (i.e.,
put the contents of the output latch on the selected pin).
PORTH<3:0> pins are digital only and tolerate voltages
up to 5.5V.
The Output Latch register (LATH) is also memory
mapped. Read-modify-write operations on the LATH
register read and write the latched output value for
PORTH.
All pins on PORTH are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.

When the external memory interface is enabled, four of
the PORTH pins function as the high-order address
lines for the interface. The address output from the
interface takes priority over other digital I/O. The
corresponding TRISH bits are also overridden.
PORTH pins, RH4 through RH7, are multiplexed with
analog converter inputs. The operation of these pins as
analog inputs is selected by clearing or setting the
PCFG<3:0> control bits in the ADCON1 register.
PORTH can also be configured as the alternate
Enhanced PWM output Channels B and C for the
ECCP1 and ECCP3 modules. This is done by clearing
the ECCPMX Configuration bit. 

PORTH is available only on 80-pin
devices.

CLRF

PORTH

; Initialize PORTH by 
; clearing output 
; data latches 

CLRF

LATH

; Alternate method 
; to clear output 
; data latches 

MOVLW

0Fh

; Configure PORTH as

MOVWF

ADCON1

; digital I/O

MOVLW

0CFh

; Value used to 
; initialize data 
; direction 

MOVWF

TRISH

; Set RH3:RH0 as inputs
; RH5:RH4 as outputs 
; RH7:RH6 as inputs